Nxp B.v.

Freescale Semiconductor,inc.

Ajay Sharma

Gopikrishna Charipadi

Rishi Bhooshan

Ashish Goel

Ruchi Bora

Umesh Pratap Singh

Sumit Varshney

Loksiva Paruchuri

Frank Martin Paglia

A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.

Method and apparatus to inject errors in a memory block and validate diagnostic actions for memory built-in-self-test (MBIST) failures

A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

System and method for reducing mutual coupling for noise reduction in semiconductor device packaging

A radio-frequency (RF) transceiver for aligning a time offset (TO) of RF signals transmitted to the RF transceiver by a user equipment (UE) includes first and second processors and first and second system memories. The first processor provides values of a cool-off period, a reset interval, a filter period, a first filter, and a primary threshold to the second processor. The second processor generates a second filter value, first and second threshold values, an instantaneous TO value, and a TO value. The second processor transmits a default TO value and a modified TO value as the TO value to the first processor during first and second time periods, respectively. The first processor generates a control signal based on the TO value. The second processor transmits the modified TO value to the UE based on the control signal.

System for alignment of RF signals

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Delhi, India

Ajay Sharma