Fujitsu Corporation

Advanced Micro Devices Corporation

Ajay Naini

Vydhyanathan Kalyanasundharam

Pranjal Srivastava

Scott A White

William Alexander Hughes

Atul Dhablania

Philip Enrique Madrid

Robert S Grondalski

James Vinh

In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

Core redundancy in a chip multiprocessor for highly reliable systems

Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Error detection in dynamic logic circuits

A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

Method and apparatus for reduction of noise sensitivity in dynamic logic circuits

A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.

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San Jose, CA, United States of America

Ajay Naini