Synopsys, Inc.

Ajay Nagarandal

Anubhav Sinha

Abhijeet Samudra

Brian Archer

Ramalingam Kolisetti

Jatin Verma

Hemasagar Babu Reddy

Saransh Nagaich

Akshay Kumar Gupta

Naresh Thakur

Milin Kaushik Raijada

Amit Kapatkar

Luis M Cruz

Kranthi Kandula

Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Deterministic data latency in serializer/deserializer-based design for test systems

An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.

High-speed functional protocol based test and debug

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Dublin, CA, United States of America

Ajay Nagarandal