Altera Corporation

Ajay Nagarandal

Bo Zhou

Jayabrata Ghosh Dastidar

Adam J Wright

Hung Hing Anthony Pang

Paul J Tracy

Binh Vo

Michael Harms

A programmable logic device such as an integrated circuit may receive user-defined configuration data from a circuit design system. The user-defined configuration data may include a minimal number of user-defined configuration variables necessary to configure the programmable logic device when combined with hardware-defined configuration variables generated in resolution engines in the programmable logic device based on the user-defined configuration variables. The resolution engines may process multiple hardware-defined configuration variables simultaneously and in parallel. A temporary storage device in the programmable logic device may store the user-defined configuration variables, the hardware-defined configuration variables, and preloaded configuration data. The resolution engines may generate a configuration bitstream to configure a configuration random access memory on the device using the configuration data stored on the temporary storage.

Constraint based bit-stream compression in hardware for programmable devices

Method and non-transitory computer-readable medium storing instructions for simulating a phase-locked loop measures a first phase of a data signal and a second phase of a reference clock signal in a phase-locked loop to be simulated, filters the first phase of the data signal by a threshold function of a lock detection module of the phase-locked loop to be simulated, and adjusts the second phase of the reference clock signal to align with the filtered first phase of the data signal.

Behavioral simulation model for clock-data recovery phase-locked loop

Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain registers that can be used to support testing. Each circuit block also has associated inputs and outputs. The inputs and outputs of the circuit blocks serve to interconnect each block to its neighboring blocks. An integrated circuit to be tested is described by a circuit netlist. The circuit netlist is processed to identify identical netlist modules. The repeating netlist modules correspond to the identical circuit blocks on the integrated circuit. By processing a given instance of a repeating netlist module, block-level test data can be generated. Global test data suitable for testing the entire integrated circuit can be generated from the block-level test data.

Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks

Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.

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Fremont, CA, United States of America

Ajay Nagarandal