Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Ajay Kumar Yadav

Faouzi Chaahoub

Georgios Asmanis

Samir Aboulhouda

Sriramkumar Sundararaman

A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

Clock-and-data recovery (CDR) circuitry for performing automatic rate negotiation

An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.

Adaptive equalizer

A data stream monitor includes an analog front end (AFE) and a digital state machine. The AFE receives recovered clock and data signals at a first rate. The AFE uses the recovered clock and a phase interpolator to generate a phase-adjusted clock signal at a second rate slower than the first rate. The AFE uses a detector operating with the phase-adjusted clock signal to generate a representation of the data signal generated from comparisons of the data signal with two reference voltages. A logical combination of the results from the comparisons generates a signal that identifies when the data signal voltage is near the common-mode voltage. The digital state machine generates a strobe signal at a third rate slower than the second rate. The strobe signal is used by the AFE to sample the signal. The sample is forwarded to the digital state machine where it is stored.

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Belmont, CA, United States of America

Ajay Kumar Yadav