Applied Materials, Inc.

Other

Applied Material, Inc.

Ajay Kumar

Brad Eaton

Wei-Sheng Lei

Madhava Rao Yalamanchili

James S Papanu

Saravjeet Singh

Padmapani Nallan

Madhavi R Chandrachood

Jungrae Park

James Matthew Holden

Anisul Haque Khan

Jeffrey D Chinn

Prabhat Kumar

Aparna Iyer

Richard Lewington

Banqiu Wu

Michael N Grimbergen

Xiaoyi Chen

Dragan Valentin Podlesnik

Sheeba J Panayil

Todd J Egan

Chentsau Chris Ying

Darin Bivens

Amitabh Sabharwal

Ibrahim M Ibrahim

Khiem K Nguyen

Omkaram Nalamasu

Mohammad Kamruzzaman Chowdhury

Guangxiang Jin

Sharma V Pamarthy

Alexander N Lerner

Wai-Fan Yau

Alan Hiroshi Ouye

Ramesh Krishnamurthy

Renee Koch

Kartik Ramaswamy

Chun Yan

Shashank C Deshmukh

Rolf A Guenther

Sanjay M Thekdi

Weinan Jiang

Wei Liu

Richard A Gross

Tong Liu

Wenguang Li

Roy C Nangoy

Virinder Grewal

Jon Christian Farr

Graeme Jamieson Scott

Jivko Dinev

Mark Wiltse

Scott Alan Anderson

Ralph Kerns

Keven Kaisheng Yu

Zhigang Mao

Chan-syun David Yang

Bruce Minaee

Shahid Rauf

Guowen Ding

Leonid Dorf

Seshadri Ramaswami

David S Mui

Ralph M Wadensweiler

Jeng H Hwang

Stephan Wege

Richard Lee

Martin S Wohlert

Ying Rui

Rohit Mishra

Simon W Tam

Mohit Kumar Jain

Jeff Chinn

Puneet Bajaj

Khalid Mohiuddin Sirajuddin

Yiqiong Wang

Wei-Te Wu

Bhanu Kalra

John Chao

Jeffrey D Chin

Axel Henke

Yeajer Arthur Chen

Changhun Lee

Katsuhisa Kugimiya

Rao Yalamanchili

Marco Mombelli

Brian Duda

Sonal A Srivastava

Apama Iyer

M Rao Yalamanchili

Chung-Huan Jeon

Jeffrey X Tran

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Wafer dicing using femtosecond-based laser and plasma etch

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, a breakthrough treatment is performed, the breakthrough treatment comprising a first physical bombardment operation, a second iterative isotropic and directional plasma etch operation, and a third directional breakthrough operation. Subsequent to performing the breakthrough treatment, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate breakthrough treatment

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process

Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.

Proximity contact cover ring for plasma dicing

Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

Light-absorbing mask for hybrid laser scribing and plasma etch wafer singulation process

Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Transfer arm for film frame substrate handling during plasma singulation of wafers

Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

Mitigation of particle contamination for wafer dicing processes

Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Hybrid wafer dicing approach using a multiple pass laser scribing process and plasma etch process

Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl, Oand at least one hydrocarbon gas in to a processing chamber, wherein the Cland Ois supplied at a Cl:Oratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

Method for improving CD micro-loading in photomask plasma etching

Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate.

Apparatus and methods for dry etch with edge, side and back protection

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Cupertino, CA, United States of America

Ajay Kumar