Synopsys, Inc.

Ajay Khoche

Timothy N Ayres

Amitava Majumdar

Dhiraj Goswami

Harbinder Singh

Denis Martin

In a multiport memory semiconductor integrated circuit, an efficient method of testing the memory for faults. The method determines a base address in a multiport memory. A plurality of addresses are scanned within the memory which are at a hamming distance of 1 from the base address, such that at least two memory cells in each column of the multiport memory device are accessed in the scan. This allows the detection of cross port faults, address mismatch faults, and bit shorts due to the fact that the faults are exposed when the two memory cells sharing access columns are accessed with test data. The method functions nominally without requiring any detailed information about the placement and routing structure of the multiport memory device.

Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information

A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.

Pre-synthesis test point insertion

A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic. Thus, the built in test circuit of the present invention is able to perform precise isolated testing on the memory block and perform precise isolated testing on the shadow logic.

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Sunnyvale, CA, United States of America

Ajay Khoche