Boston University

Lightmatter, Inc.

Other

Freescale Semiconductor,inc.

Ajay Joshi

Nicholas Christopher Harris

Darius Bunandar

Shashank Gupta

Mykhailo Tymchenko

Rashmi S Agrawal

Bradford Turcott

Ravindraraj Ramaraju

Michael Gould

Thomas Bartos

Robert A Turner

Bennett B Goldberg

Anthony Kopa

M Selim Unlu

Carlos Dorta-Quinones

Kurt M Marshek

Anders Bitsch-Larsen

Ronen Adato

James Carr

Robert Turner

Binoy Shah

Reza Baghdadi

Bobak A Nazer

Gregory Schmidt

Daniel Leonardi

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Photonic communication platform and related architectures, systems and methods

A computing system includes accelerator devices for hardware acceleration of operations of a fully homomorphic encryption (FHE) application, including a hybrid bootstrapping operation that may be parallelized for increased performance. Hybrid bootstrapping includes a first extraction on a first ciphertext (e.g., Ring Learning with Errors or RLWE) to form a plurality of second ciphertexts (e.g., LWE) corresponding to respective elements of the encrypted data, and a plurality of blind-rotate operations performed independently on the respective second ciphertexts to collectively produce a plurality of third ciphertexts (e.g., RLWE). A second extraction of respective elements of the third ciphertexts forms a plurality of fourth ciphertexts (e.g., LWE), and a repacking of respective elements of the fourth ciphertexts recreates the first-ciphertext representation of the encrypted data with restored modulus and reduced noise.

Computing system for fully homomorphic encryption applications using parallelizable hybrid bootstrapping

Photonic communication platform and related methods for increasing yield

An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.

Semi-custom accelerator device for bootstrappable fully homomorphic encryption

Optical verification testing of an IC includes obtaining images of the IC by, for each image: (i) illuminating the IC with excitation light, wherein the excitation light corresponds to a respective specific optical excitation of a predefined spectrum of optical excitations (e.g., wavelength spectrum); and (ii) detecting scattered light from the IC in response to the specific optical excitation. For each of a set of sub-regions of the images, the respective sub-region is mapped to at least one of (i) a specific sub-unit of a predefined set of sub-units (e.g., gates) of the IC and (ii) a null result, thereby creating a representation of a detected layout of the IC as an arrangement of the sub-units. The representation can be used to verify that an as-fabricated layout is consistent with an as-designed layout, to detect unauthorized modifications of the IC structure.

Gate-level mapping of integrated circuits using multi-spectral imaging

A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.

Hierarchical error correction

A golf club for impelling a golf ball further with thrust force assist. Pressurized fluid from a fluid pump enters the club through the handle assembly and exits out through a fluid nozzle at the back of the club head. The club thus prepared is swung in the normal way. Due to the added thrust force, the club head velocity is greater than it would be without any assist, causing the ball to be impelled further down the fairway and/or teaching the golfer to swing faster. The club further includes a triggering mechanism to control the flow of fluid into the club.

Thrust powered golf club

Growing community of inventors

Lexington, MA, United States of America

Ajay Joshi