Qualcomm Incorporated

Ajay Anant Ingle

Lucian Codrescu

Erich Plondke

Marc M Hoffman

Christopher E Koob

Suresh Kumar Venkumahanti

Mao Zeng

Sujat Jamil

Paul Bassett

Muhammad Ahmed

Deepak Mathew

Jian Shen

Jose Fridman

Charles Joseph Tabony

Jentsung Lin

Eric W Mahurin

Baker Mohammad

David J Hoyle

Evandro Carlos Menezes

Robert Allan Lester

Jianming Zhu

Muhammad Tauseef Rab

Rahul R Toley

Yurong Sun

Jen Tsung Lin

Eai-Hsin Alfred Kuo

Michael John Lopez

Jun Ho Bahn

Erich J Plondke

Marc Murray Hoffman

Sujat c/o Qualcomm Incorporated Jamil

Eric Wayne Mahurin

Saurabh Kulkarni

Erich James Plondke

Muhammad T Rab

Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

Mixed-width SIMD operations using even/odd register pairs for wide data elements

An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

System and method for piecewise linear approximation

An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.

FIFO load instruction

Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors

A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

System and method of processing hierarchical very long instruction packets

An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

Arbitrary size table lookup and permutes with crossbar

An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Vector indirect element vertical addressing mode with horizontal permute

Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Vector register addressing and functions based on a scalar register data value

Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Systems and methods of data extraction in a vector processor

A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Selective coupling of an address line to an element bank of a vector register file

A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.

Memory management unit directed access to system interfaces

An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Device and method for computing a channel estimate

An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Table call instruction for frequently called functions

In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.

System and method for generating and using predicates within a single instruction packet

A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.

Growing community of inventors

Austin, TX, United States of America

Ajay Anant Ingle