Texas Instruments Corporation

Ajai Paulose

Aravind Ganesan

Jaiganesh Balakrishnan

Jawaharlal Tangudu

Neeraj Shrivastava

Pankaj Gupta

Jagannathan Venkataraman

Nagarajan Viswanathan

Sreenath Narayanan Potty

Yeswanth Guntupalli

Mathews John

Chandrasekhar Sriram

Aswath Vs

Himanshu Varshney

Raju Kharataram Chaudhari

Divyeshkumar Mahendrabhai Patel

Girish Nadiger

Shabbar Abbasi Vejlani

Mahesh Ravi Varma

Ankur Jain

Ankush G P

A system includes: a first device; and a second device coupled to the first device. The second device has a receiver. The receiver has a comparator and a controller. The comparator has an adjustment terminal. The controller has an input and an output. The output of the controller is coupled to the adjustment terminal of the comparator. The controller is configured to: obtain an offset estimation model; receive an input voltage at its input; determine a comparator offset responsive to the offset estimation model and the input voltage; and provide an adjustment control signal to its output responsive to the determined comparator offset.

Indirect comparator offset estimation

A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

Equalizer adaptation for data link

An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

High order nonlinearity estimation of radiofrequency analog-to-digital converters

A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

Non-linearity correction

A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Flexible and efficient device trim support using eFuse

Flexible and efficient device trim support using efuse

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Idukki, India

Ajai Paulose