Hewlett-packard Company

Semiconductor Components Industries, LLC

Avago Technologies General IP (singapore) Pte. Ltd.

Hewlett-packard Corporation

Micron Technology Incorporated

Agilent Technologies, Inc.

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Airell Richard Clark, Ii

Dwight Poplin

Todd Stephen Sachs

Brian R Jung

Michael J Zelman

Daryl E Anderson

Gadiel Seroussi

Timothy F Brown

Vamsi K Srikantam

Billy E Thayer

Donald M Reid

Jeffrey P Tobin

Jeffrey A Hintzman

Ignacio Jose Perez

Agustin B Hernandez

Matthew P Heineck

Richard Wesley Garvin

Donald Montgomery Reid

Various embodiments of the present technology may comprise methods and apparatus for error detection in an imaging system. The method and apparatus may comprise pixels arranged in rows and columns and an error detection circuit receiving pixel data generated by the pixels. The error detection circuit may detect errors and generate an error condition and/or signal, for example if one or more image frames are the same and/or a readout error has occurred.

Methods and apparatus for error detection in an imaging system

Various embodiments of the present technology may comprise a method and apparatus for pixel readout. The method and apparatus may comprise a pixel array capable of reading out one or more non-rectilinear subsets of the pixel array to form a non-rectilinear primary image. The one or more non-rectilinear subsets may be selected according to a desired rectilinear output image, wherein the rectilinear output image is formed using only the one or more subsets. The primary image may then be transformed to form the rectilinear output image.

Methods and apparatus for selective pixel readout for image transformation

An image device, such as a digital camera, detects specific repeating patterns of signal variations by processing columnar information from the device's two-dimensional sensor array used to generate images. In one embodiment, the columnar information is derived from calculating row averages for two image frames, with each row average being a computed average of the multiple signal intensities generated from some or all of the sensors within a particular row. After the columnar information is determined for each of the two frames, a difference signal is generated as a sequence of the differences between the row averages for the first frame and the row averages for the second frame. This row averaging and frame differencing removes a large percentage of the signal energy that is not a result of the artifact of interest, such as the flicker generated by illumination having intensity fluctuations at 100 Hz or at 120 Hz. In some embodiments of the invention, the row averaging and/or the frame-to-frame comparison are deleted.

Automatic flicker frequency detection device and method

Disclosed are various systems, devices and methods for digital camera image stabilization. In one embodiment, a digital camera captures a plurality of digital images of a subject simultaneously or near-simultaneously and stores the captured images in memory as individual digital data sets. While the digital images are being captured simultaneously or near-simultaneously by means of a plurality of rolling shutters, a relative position determination device such as an angular rate sensor is employed to sense and save to memory data representative of the relative positions of the digital camera at the moments the individual digital images or frames are being exposed. Spatial shift directions and magnitudes are calculated in a processor of the camera on the basis of such data, and then applied to the individual data sets to form aligned data sets comprising aligned data points. To compensate for camera shake occurring while the individual images were being captured, the aligned data sets are added together to form an output data set representative of an output image.

Systems, devices and methods for digital camera image stabilization

Methods, systems, and computer programs for encoding images are described. In one aspect, quantized frequency domain vectors are sequentially generated from a sequence of blocks of the image. Each quantized frequency domain vector includes a set of quantized forward transform coefficients that are derived from a respective image block. For each successive quantized frequency domain vector, a current input capacity level of a buffer is determined and the quantized frequency domain vector is modified to increase compressibility when the current input capacity level is determined to be below a prescribed threshold. Modified and unmodified quantized frequency domain vectors are encoded into a sequence of encoded image blocks. The sequence of encoded image blocks is stored in the buffer.

Image encoding with dynamic buffer-capacity-level-based compression adjustment

A clock gating circuit reduces the power dissipation in a digital circuit including at least one functional block by gating the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives a clock signal and a clock disable signal generated by the functional block, and gates the clock signal at the input to the clock tree feeding the functional block. Further, a global signal generator is provided to transmit a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.

Method and apparatus for clock gating clock trees to reduce power dissipation

A method and apparatus for prioritizing encoded MATCH signal and MATCH ADDRESS signals for a content addressable memory ('CAM') array is disclosed. Each CAM core has an output encoder for providing a MATCH signal and, if a MATCH is determined, a MATCH.sub.-- ADDRESS signal indicative of locations in the CAM of the data of interest. The priority encoder output signals are encoded to provide a final MATCH signal and a final MATCH.sub.-- ADDRESS to only the highest priority MATCH.sub.-- ADDRESS from the CAM core having the data, solving the problem of determining which of a plurality of CAM matches to select.

Match and match address signal prioritization in a content addressable

A computer memory system provides self-timed precharging and output signal latching. The method and apparatus are useful in accelerating search cycles for associative data in a memory such as a content addressable memory (CAM) where single transition memory search and output signal encoding is required. Feedback is provided to initiate memory precharging as soon as an actual search of the memory ends rather than at a next system clock transition.

Method and apparatus for self-timing associative data memory

A method and apparatus for encoding MATCH signal and MATCH ADDRESS signal generation for a content addressable memory ('CAM') array is disclosed. Each CAM core has an output encoder for providing a MATCH signal and, if a MATCH is determined, a MATCH.sub.-- ADDRESS signal indicative of the location in the CAM of the data of interest. In order to speed the critical search path, each signal line for the MATCH and MATCH.sub.-- ADDRESS have the same number of transistors, with designated MATCH.sub.-- ADDRESS transistors being used to indicate a MATCH, that is, providing a substitute MATCH signal, if the MATCH line has no transistor. The output encoder output signals are encoded to provide a final MATCH signal and a final MATCH.sub.-- ADDRESS which adds a CAM core designator to the MATCH.sub.-- ADDRESS from the CAM core having the data.

Match and match address signal generation in a content addressable

An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of reference signals generated from a system voltage. A delay line is varied based upon the comparison results, generating a delayed timing signal related to PVT fluctuations.

PVT self aligning internal delay line and method of operation

A method of compressing a stream of raw data including the steps of providing a memory device having compression active state and a compression inactive state, inputting a raw data segment into the memory device, generating a compressed data segment based on the raw data segment, creating output data based on the compressed data segment when the memory device is in the compression active state, otherwise based on the raw data segment when in the memory device is the compression inactive state, calculating a compression coefficient, and setting the state of the memory device based on the compression coefficient, such that compressed data is output only when compression has recently proven effective, and raw data is output when compression has recently proven ineffective. The method may also include decompression of the output data.

Data compression method and apparatus with optimized transitions between

An apparatus and method for parallel data compression and decompression uses packing and unpacking of data which has multi-variable components, for example, relational multi-variable content data such as tristimulus color space data used in color hard copy applications. Multiple input words are compressed in parallel compression engines and fed in parallel to a packer device which configures the codes in an order determined by order of compression and byte count for each word into a single bit string code. In the decompression cycle of the process, an unpacker device separates the single bit string code based upon length of a data string represented by a code word last decoded by either the decompression engine for that code word if the decompression engine is idle, or the length of the string that has been decoded so far if the decompression engine is currently working on a code.

Parallel data compression and decompression

A class of lossless data compression algorithms use a memory-based dictionary of finite size to facilitate the compression and decompression of data. To reduce the loss in data compression caused by dictionary resets, a standby dictionary is used to store a subset of encoded data entries previously stored in a current dictionary. In a second aspect of the invention, data is compressed/decompressed according to the address location of data entries contained within a dictionary built in a content addressable memory (CAM). In a third aspect of the invention, the minimum memory/high compression capacity of the standby dictionary scheme is combined with the fast single-cycle per character encoding/decoding capacity of the CAM circuit. In a fourth aspect of the invention, a selective overwrite dictionary swapping technique is used to allow all data entries to be used at all times for encoding character strings.

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Albany, OR, United States of America

Airell Richard Clark, Ii