Mitsubishi Electric Engineering Company, Limited

Other

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Aiko Nishino

Katsumi Dosaka

Naoya Watanabe

Hisashi Iwamoto

Wataru Sakamoto

A main control circuit generates a plurality of main control signals of different phases to local control circuits. The local control circuits produce row-related control signals greater in number than the main control signals in accordance with these main control signals. A semiconductor memory device can be easily adapted to change in bank structure, and can perform a fast and stable operation with a low current consumption.

Semiconductor memory device

Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially transferred to transfer control circuit. Transfer control portion converts the serially transferred link information to parallel information, and transfers the parallel information to latch circuits arranged in the core circuit and corresponding to circuits requiring the LT link information. An influence on an interconnection layout by laser trimmable link elements is eliminated.

Semiconductor integrated circuit device having efficiently arranged link program circuitry

Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential

An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.

Output circuit and synchronous semiconductor memory device having a

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Hyogo, Japan

Aiko Nishino