Zte Corporation

Sanechips Technology Co., Ltd.

Aijun Li

Lu Zhang

Lei Guo

Xiaojun Zhou

Wenqiong Lin

Hongbing Pan

Qin Liu

Yimin Xi

Mengxiao Wang

Weiliang Lian

Deyong Zeng

Guanjun Li

Zhimin Yan

A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.

Vector operation core and vector processor

The present invention discloses a Softswitch and system for implementing the intelligent network in the next generation networks and a method for interconnecting the intelligent networks to the PSTN. The Softswitch comprises: a network adaptive device for implementing the communication between the Softswitch and other devices in said network, as well as receiving the call request; a call server for determining whether the call received by said network adaptive device is a common call or the call of the intelligent network and processing the common call; and an INAP adapter for responding the call of the intelligent network and encoding/decoding the INAP message.

Implementation of the intelligent network in the next generation networks and its interconnection to the PSTN

Growing community of inventors

Shenzhen, China

Aijun Li