Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Analog Devices,inc.

Aiguo Yan

Liang Ma

Marko Kocic

Deepak Mathew

Timothy Perrin Fisher-Jeffes

Bernard Mark Tenbroek

Jonathan Richard Strange

John Zijun Shen

Carsten Aagaard Pedersen

Lidwine Martinot

Thomas James Barber, Jr

Yonggang Hao

Paul Donald Krivacek

Eric Aardoom

Zoran Zvonar

Ayman Shabra

Timothy Fisher-Jeffes

Songsong Sun

Krishnan Vishwanathan

Abhay Sharma

Palle Birk

Jianwei Zhang

Navid Fatemi-Ghomi

Thomas Keller

David Stephen Ivory

Jason Taylor

Pier Bove

Thomas Barber

Thomas J Barber

Blind channel impulse response combining for noise mitigation in channel estimation in a TD-SCDMA receiver includes applying a correlation function to pairs of channel impulse response windows associated with non-desired user equipments, grouping all those channel impulse response windows having a correlation function above a predetermined threshold as identified with the same user equipment, and combining the channel estimation results from each identified user equipment in the group to mitigate noise.

Method and system for blind channel impulse response combining for noise mitigation in channel estimation in a TD-SCDMA receiver

A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2&#xd7; or higher.

Advanced joint detection in a TD-SCDMA system

A channel impulse response (CIR)/DC offset (DCO) joint estimation for a time division synchronous code division multiple access (TDSCDMA) system includes generating from a basic midamble and received midamble an initial estimation of the CIR as a series of CIR taps; storing the initially estimated CIR taps; calculating a DC compensated CIR from the initially estimated CIR taps; filtering out the noise from the DC compensated CIR to produce the CIR estimation; and calculating the DC offset estimation from the CIR estimation.

Channel impulse response (CIR)/DC offset (DCO) joint estimation block and method

A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1&#xd7; and 2&#xd7; oversampling rates by sending to the JD block a second input signal.

Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver

The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2&#xd7;. Interpolation filters are used to increase the data rate to a higher data rate, such as 8&#xd7;. Decimation filters are used to reduce the data rate from a higher rate, such as 8&#xd7;, to a lower rate, such as 2&#xd7;. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2&#xd7;) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.

Filters for communication systems

A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

Interface between chip rate processing and bit rate processing in wireless downlink receiver

Re-quantization in downlink receiver bit rate processor

A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.

Data flow control in wireless communication systems

A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.

Receiver architecture

An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Multi-mode bit rate processor

A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.

Parameter estimation for modulated signals

A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

Architecture for joint detection hardware accelerator

A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

Fixed-point implementation of a joint detector

A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

Pre-scaling of initial channel estimates in joint detection

A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

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North Andover, MA, United States of America

Aiguo Yan