University of Southern California

Aiguo Xie

Peter A Beerel

Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called &ldquo;bad cycles&rdquo; which are encountered in many formal verification problems.

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Alhambra, CA, United States of America

Aiguo Xie