Lsi Logic Corporation

Lsi Corporation

Aiguo Lu

Ivan Pavisic

Elyar Eldarovich Gasanov

Andrej A Zolotykh

Ranko L Scepanovic

Andrey Nikitin

Cheng-Gang Kong

Sandeep Bhutani

Hui-Yin Seto

Ilya Viktorovich Lyalin

Nikola Radovanovic

Igor V Kucherenko

William Lau

Andrej Zolotykih

Alexander Andreev

Pedja Raspopovic

Sergej B Gashkov

Dusan Petranovic

Andrej A Zolotykj

A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Method and computer program for generating grounded shielding wires for signal wiring

A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Method and apparatus for balancing signal delay skew

A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Signal delay skew reduction system

A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

Optimizing IC clock structures by minimizing clock uncertainty

A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.

Method of buffer insertion to achieve pin specific delays

Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at least one function associated with the carry module based on a variable k derived from a Fibonacci series. Invertor, XOR, XNOR (more preferably, OR(NOT(a),b)) and multiplexer elements are selectively coupled to the input and output modules to configure the adder based circuit as a subtractor, adder-subtractor, incrementor, decrementor, incrementer-decrementor or absolute value calculator. A computer process of designing the adder base circuit recursively expands the functions, and optimization of death, fanout and distribution of negations is performed.

Optimization of adder based circuit architecture

The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Method to find boolean function symmetries

A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations. Cost functions are calculated for each pin based on setup and hold time violations, and are selectively applied to the resynthesis steps.

Process of restructuring logics in ICs for setup and hold time optimization

A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.

Floor plan tester for integrated circuit design

A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n&equals;OR(h_k, AND(v_k, h_&lcub;n&minus;k&rcub;)) and v_n&equals;AND(v_k, v&lcub;n&minus;k&rcub;), where k&equals;F_l and n&minus;k&equals;F_&lcub;l&minus;1&rcub;, satisfies F_l<n&equals;F_&lcub;l&plus;1&rcub;, &lcub;F_l&rcub; is a Fibonacci series and n is the number of bits of an input to the circuit. In one form, the circuit is a comparator having output functions h_n and v_n that depend from input functions U&lsqb;i&rsqb;&equals;AND(NOT(A&lsqb;i&rsqb;), B&lsqb;i&rsqb;) and V&lsqb;i&rsqb;&equals;OR(NOT(A&lsqb;i&rsqb;), B&lsqb;i&rsqb;), where A&lsqb;i&rsqb; and B&lsqb;i&rsqb; are inputs to the comparator, and functions h_n, v_n defined as h_n&equals;h_n(U&lsqb; &rsqb;, U&lsqb; &rsqb;, V&lsqb; &rsqb;, . . . , U&lsqb;n&minus;1&rsqb;, V&lsqb;n&minus;1&rsqb;)&equals;OR(U&lsqb;n&minus;1&rsqb;, AND(V&lsqb;n&minus;1&rsqb;, U&lsqb;n&minus;2&rsqb;), . . . , AND(V&lsqb;n&minus;1&rsqb;, . . . , V&lsqb; &rsqb;, U&lsqb; &rsqb;)), and v_n&equals;v_n(V&lsqb; &rsqb;, . . . , V&lsqb;n&minus; &rsqb;)&equals;AND(V&lsqb; &rsqb;, . . ., V&lsqb;n&minus;1&rsqb;). In one form, the comparator includes an LEQ input that identifies strict or non-strict inequality comparison by the comparator. The depth is further minimized by a distribution of negations of elements forming the circuit. A computer process is described to carry out the design, including mapping 2-input elements from a cell library of 3-input elements.

Optimization of comparator architecture

A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.

Assignment of cell coordinates

Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.

Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells

A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).

Netlist resynthesis program based on physical delay calculation

A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.

Growing community of inventors

Cupertino, CA, United States of America

Aiguo Lu