Southeast University

Aiguo Bu

Chao Wang

Jie Li

Na Bai

Chen Hu

Ming Ling

A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Growing community of inventors

Jiangsu, China

Aiguo Bu