Fungible, Inc.

Juniper Networks, Inc.

Microsoft Technology Licensing, LLC

Aibing Zhou

Pradeep S Sindhu

Deepak Goel

Wael Noureddine

Srihari Raju Vegesna

Felix A Marti

Jean-Marc Frailong

Shashi Kumar

Rohit Sunkam Ramanujam

Rajan Goyal

Bertrand Serlet

Paul Kim

David James Ofelt

Dmitriy Leonidovich Budko

Gaurav Gupte

Hoai Vu Thanh Tran

Aravind Vidhyasagar Lappasi

Leith Alan Leedom

Chang-Hong Wu

John Delmar Johnson

Dongping Luo

Rajesh Nair

Xianzhi Li

Hongsheng Ping

Wing Leong Poon

Rajesh G Nair

Techniques are described for providing a scaled-out transport supported by interconnected data processing units (DPUs) that operates as a single system bus connection proxy for device-to-device communications within a data center. As one example, this disclosure describes techniques for providing a Peripheral Component Interconnect Express (PCIe) proxy for device-to-device communications employing the PCIe standard. The disclosed techniques include adding PCIe proxy logic on top of a host unit of a DPU to expose a PCIe proxy model to application processors, storage devices, network interface controllers, field programmable gate arrays, or other PCIe endpoint devices. The PCIe proxy model may be implemented as a physically distributed Ethernet-based switch fabric with PCIe proxy logic at the edge and fronting the PCIe endpoint devices. The interconnected DPUs and the distributed Ethernet-based switch fabric together provide a reliable, low-latency, and scaled-out transport that operates as a PCIe proxy.

Scaled-out transport as connection proxy for device-to-device communications

This disclosure describes techniques for performing communications between devices using various aspects of Ethernet standards. As further described herein, a protocol is disclosed that may be used for communications between devices, where the communications take place over a physical connection complying with Ethernet standards. Such a protocol may enable reliable and in-order delivery of frames between devices, while following Ethernet physical layer rules, Ethernet symbol encoding, Ethernet lane alignment, and/or Ethernet frame formats.

Reliable communications using a point to point protocol

An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Access node for data centers

A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.

Access node integrated circuit for data centers which includes a networking unit, a plurality of host units, processing clusters, a data network fabric, and a control network fabric

A network device includes a receiver component that generates flow control information. The network device also includes a transmitter component that receives a packet for forwarding to the receiver component, receives flow control data for the packet from the receiver component, and provides the packet and the flow control data for the packet to a fabric component. The fabric component performs a congestion management operation for the packet, and forwards the packet to the receiver component based on the flow control data and results of the congestion management operation.

Oversubscribed packet stream-based interconnect protocol

A network device receives traffic associated with a network of intermediate network devices and user devices, classifies the received traffic, and allocates the classified traffic to traffic queues. The network device also schedules particular queued traffic, provided in the traffic queues and bound for particular intermediate network devices, using a hybrid weighted round robin (WRR) scheduler where the hybrid WRR scheduler schedules the particular queued traffic according to one of a 1-level WRR schedule, a 1.5 level WRR schedule, or a 2-level WRR schedule. The network device further provides the particular queued traffic to the particular intermediate network devices based on the scheduling of the hybrid WRR scheduler.

Hybrid weighted round robin (WRR) traffic scheduling

A system and method for intrusion detection and prevention processing are described. Spin state information associated with a signature may be prefetched by a network device having one or more buffers. The spin state information may be stored by the buffer. Context data may be searched using the spin state information stored by the buffer.

Hardware-based intrusion detection accelerator

Techniques are described for detecting corruption of buffer pointers passed between a local processor and a remote processor on a network device. For example, the first processor, which may be a memory controller, receives and stores packets within memory. A second processor, such as a host processor for the network device, is coupled to the first processor by a bus. The first processor communicates a memory pointer associated with an a given packet to the second processor for processing of the packet, and maintains a backup copy of the memory pointer. Upon receiving the memory pointer back from the second processor, the first processor compares at least a portion of the memory pointer received from the second processor with an equivalent portion of the copy of the memory pointer to determine whether the received memory pointer has been corrupted.

Detection of corrupted memory pointers within a packet-processing device

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San Jose, CA, United States of America

Aibing Zhou