Taiwan Semiconductor Manufacturing Comp. Ltd.

Ai-Tee Ang

Chung-Shi Liu

Ming-Da Cheng

Hsiu-Jen Lin

Kuei-Wei Huang

Chih-Wei Lin

Wei-Hung Lin

Meng-Tse Chen

Yu-Peng Tsai

Tsai-Tsung Tsai

Hui-Min Huang

Wei-Yu Chen

Ching-Hua Hsieh

Cheng-Ting Chen

Shing-Chao Chen

Ching-Yao Lin

Wen-Hsiung Lu

Chun-Cheng Lin

Cheng-Chung Lin

Hsuan-Ting Kuo

Yu-Jen Tseng

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Package-on-package structure including a thermal isolation material

A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Package-on-package structure

System for processing semiconductor devices

A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

Manufacturing method of integrated fan-out package

Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having at least one recess configured to accept and retain at least one unit. The at least one recess is aligned over, and configured to hold the at least one unit over, at least a portion of the at least one unit retainer. The cover is retained to the device processing boat by the at least one unit retainer. At least one pressure sensor having at least one sensel is disposed in the base. The sensel is configured to sense a clamping force applied by the cover to the at least one unit.

Semiconductor processing boat design with pressure sensor

Package on-package structure

Package on-package structure including a thermal isolation material and method of forming the same

An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.

Integrated fan-out package and manufacturing method thereof

Systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a system for processing semiconductor devices includes a radiation energy source, a support, and a tool disposable between the support and the radiation energy source. The tool includes apertures adapted to retain a package component over the support. The system includes a cooling device proximate the support.

Systems for processing semiconductor devices, and methods of processing semiconductor devices

A device comprises a top package mounted on a bottom package, wherein the bottom package comprises a plurality of interconnection components and the bottom package comprises a plurality of first bumps formed on a first side of the bottom package, a semiconductor die is bonded on a second side of the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnection components and the semiconductor die is located between the top package and the bottom package, and an underfill layer formed between the top package and the bottom package.

Growing community of inventors

Hsin-Chu, Taiwan

Ai-Tee Ang