Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

United Microelectronics Corp.

Au Optronics Corporation

Lextar Electronics Corporation

Ai-Sen Liu

Chia-Hui Lin

Cheng-Chung Lin

Baw-Ching Perng

Ming-Ta Lei

Yih-Shung Lin

Syun-Ming Jang Jang

Yu-Liang Lin

Henry Lo

Wen-Kai Wan

Chin-Fu Lin

Bin-Siang Tsai

Kuei-Wu Huang

Ping-Hsu Chen

Ping Chuang

Yu-Huei Chen

Shang-Ting Tsai

Chao-Jung Chang

Yih-Hsiung Lin

Li-Jui Chen

Mei Sheng Zhou

Cheng-Lin Huang

Chun-Yuan Wu

Ru-Shi Liu

Chung-Long Chang

Yen-Chen Chen

Ming-Chi Hsu

Kuo-Chih Lai

Chih-Hao Lin

Mei-Sheng Zhou

Po-Lun Chen

Chun-Hsien Lin

Jian-Chin Liang

Sunny Wu

Jo-Hsiang Chen

Chun-Ling Lin

Yung-Fu Chang

Tzu-Yuan Lin

Yang-Ju Lu

Jin-Jei Wu

Ko-Wei Lin

Jen-Po Huang

Shune-Long Wu

Ren-Hung Huang

Po-Chang Wu

Hui-Ru Wu

Meng-Chyi Wu

Seng Wah Liau

Xu Yang Shen

Chun Che Lin

Chong-Long Ho

Chia-Hsing Sun

Chun Hsien Lin

Ling-Ling Wei

Shwu-Yun Tsay

Gorge Huang

Tony Lu

Gnesh Yeh

Candy Liang

Sunny Su

Ming-Dai Lei

Shih Che Wang

The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Display device

A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.

Non-volatile memory and forming method thereof

A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Method for fabricating a MIM capacitor

A phosphor, having a general formula of K[SiGe]F:Mn. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(I/I)*100%, Iand Iare the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K&#x3c;T&#x2264;470K.

Phosphor

An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.

Transparent conductive structure, device comprising the same, and the manufacturing method thereof

A method of fabricating an epitaxial device, comprising: providing a substrate having a first surface and a normal direction; epitaxially forming a first transition layer in a first temperature on the first surface of the substrate and in-situ incorporating a porogen into the first transition layer; and adjusting the first temperature to a second temperature to burn out the porogen from the first transition layer to form a hollow component inside the first transition layer.

Method of fabricating an optoelectronic device with a hollow component in epitaxial layer

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Surface treatment of metal interconnect lines

An LCD panel including a first substrate, a second substrate and a smectic liquid crystal layer is disclosed. The first substrate includes a first electrode, a second electrode and a first horizontal alignment film. The first electrode has plural first portions. The second electrode has plural second portions. The first portions are spaced by the second portions. The electrical field directions formed between the first portions and the second portions are perpendicular to the surface of the first substrate. The electrical field direction on each first portion is opposite to that on each second portion. The first horizontal alignment film covers the first and the second electrodes. The second substrate includes a second horizontal alignment film. The horizontal rubbing direction of the first horizontal alignment film is parallel to that of the second horizontal alignment film. The smectic liquid crystal layer is sealed between the first and the second substrates.

Fringe field switching LCD having smectic liquid crystal and utilizing alternate current squared wave driving voltage

A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.

Micro-etching method to replicate alignment marks for semiconductor wafer photolithography

A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Surface treated low-k dielectric as diffusion barrier for copper metallization

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Method for multiple spacer width control

A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3&#x3c3; variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

Advanced process control approach for Cu interconnect wiring sheet resistance control

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Method for forming multiple spacer widths

A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow. A second silicon carbide barrier layer is formed to cover the recess and above the low-k dielectric layer and the first silicon carbide barrier layer so as to seal the top of the structure. A portion of the second silicon carbide barrier layer above the low-k dielectric layer is converted with an oxidation treatment into a layer of silicon oxide. The layer of silicon oxide is then removed and the metal conductive layer is fully encapsulated by the silicon carbide barrier layer.

Method for forming dielectric barrier layer in damascene structure

Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Growing community of inventors

Hsinchu, Taiwan

Ai-Sen Liu