Intel Ndtm US LLC

Ahsanur Rahman

Shantanu R Rajwade

Sagar Upadhyay

Chang Wan Ha

Tzu-Ning Fang

Rezaul Haque

Narayanan Ramanan

Tarek Ahmed Ameen Beshari

Matin Amani

Netra Mahuli

Binh Ngo

Pratyush Chandrapati

Bayan Nasri

Dhanashree R Kulkarni

Radhika Chinnammagari

Seong Je Park

A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.

Efficient bitline stabilization for program inhibit in NAND arrays

A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

Memory cell sensing circuit with adjusted bias from pre-boost operation

Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.

Grouped global wordline driver with shared bias scheme

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Folsom, CA, United States of America

Ahsanur Rahman