Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Ahreum Kim

Minsu Kim

Youngo Lee

Seungman Lim

Eunhee Choi

Ansoo Park

Chunghee Kim

Homoon Shin

Sunghoon Kim

Hyun Yeul Lee

Daeseok Byeon

Youngjae Kim

Yongsung Cho

Hyun Shik Lee

Yunki Baek

Dae Seong Lee

Yongjun Jang

Gigeun Kim

Chanhee Park

Jincheol Kim

Dooho Cho

Daeseong Lee

Jongkyu Ryu

A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

Flip flop and design method for integrated circuit including same

An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.

Active resistor array of semiconductor memory device

A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

Multi-bit flip-flop and integrated circuit including the same

A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.

Semiconductor device

An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

Integrated circuit including flip-flop and computing system for designing the integrated circuit

A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.

Flip flop and design method for integrated circuit including the same

A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

Voltage level shifter cell and integrated circuit including the same

A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.

Memory device including row decoders

A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

Integrated clock gating cell and integrated circuit including the same

In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

Clock gating cell with low power and integrated circuit including the same

An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.

Integrated clock gating circuit

A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.

Semi-dynamic flip-flop implemented as multi-height standard cell and method of designing integrated circuit including the same

An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

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Daegu, South Korea

Ahreum Kim