Drexel University

Intel Corporation

Stony Brook University

Ahmet Can Sitik

Baris Taskin

Ankit More

Emre Salman

Weicheng Liu

Technologies for node-degree based clustering include a computing device to construct a graph that includes multiple vertices corresponding to the data points of a data set. The computing device inserts an edge between each pair of vertices that has a corresponding similarity metric that meets a predetermined threshold similarity metric. The computing device determines a node degree for each vertex in the graph and initializes a cutoff node degree as the lowest node degree of the vertices. The computing device selects a test subset of the graph that includes vertices having a node degree less than or equal to the cutoff node degree. The computing device determines whether the test subset covers the graph and if not increases the cutoff node degree. If the test subset covers the graph, the data points corresponding to the vertices of the test subset are the representative cluster. Other embodiments are described and claimed.

Technologies for node-degree based clustering of data sets

A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

Slew-driven clock tree synthesis

One aspect of the invention provides a including: (a) placing N&#xd7;N max size buffers at an (n&#x2212;1)st level of one of the voltage domains i until a maximum slew slewwithin the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.

Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits

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Hillsboro, OR, United States of America

Ahmet Can Sitik