Texas Instruments Corporation

Other

Globalfoundries Inc.

Nvidia Corporation

Icera, Inc.

Sirific Wireless Corporation

Ahmed Reda Fridi

Abdellatif Bellaouar

Seydou Nourou Ba

Arul Balasubramaniyan

Sher Jiun Fang

Hamid Safiri

Sherif Embabi

Khaled M Sharaf

Man Tran

The present disclosure relates to a structure including an adaptive noise canceller circuit which is configured to suppress noise in a feedback sigma-delta modulator circuit and provide real-time tracking of a noise cancellation signal.

Adaptive noise cancellation

A transceiver includes a frequency modulation continuous wave generator to generate a frequency sequence and a digital phase locked loop to generate a waveform based on the frequency sequence. The digital phase locked loop includes a plurality of control registers. A main controller captures a reference state defined in the plurality of configuration registers prior to the frequency sequence, initiates the frequency sequence, restores the reference state of the configuration registers after completion of the frequency sequence, and repeats the frequency sequence after restoring the reference state.

Method and system for generating a saw-tooth signal with fast fly back interval

A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.

Automatic loop-bandwidth calibration for a digital phased-locked loop

A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Method and system for calibrating a frequency synthesizer

A phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined advantageously via dual varactors within a voltage controlled oscillator to further reduce loop filter components. The PLL removes the drawbacks of noise introduced by circuitry normally used for summing dual path configurations.

Type II phase locked loop using dual path and dual varactors to reduce loop filter components

A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer ( ) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation ( ) and an interpolation tuning implementation ( ) are also described.

Method for tuning a VCO using a phase lock loop

A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node ( ) to a first voltage level after a sample period ( ) has occurred. After the ramp node ( ) is charged to the first voltage level, the ramp node is charged to a second voltage level during period ( ). By precharging the ramp node ( ) during the hold period ( ), it reduces any leakage current in the SH switch ( ), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector ( ).

Sample and hold phase detector having low spurious performance and method

The present invention discusses fractional compensation timing circuitry (,) to track a VCO output frequency, f,, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.

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Richardson, TX, United States of America

Ahmed Reda Fridi