Micron Technology Incorporated

Ahmed Nayaz Noemaun

Gordon A Haller

Stephen W Russell

Amitava Majumdar

Shawn D Lyonsmith

Qianlan Liu

Steve K McCandless

Pradeep Ramachandran

Ted Lyle Taylor

Santanu Sarkar

Durga Prasanna Panda

Tao D Nguyen

Zia Alan Shafi

Luca Laurin

Sara Vigano

Michael J Irwin

Chandra S Danana

Rekha Chithra Thomas

A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.

System for predicting properties of structures, imager system, and related methods

Stacks of electrically resistive materials and related apparatuses, electrical systems, and methods are disclosed. An apparatus includes one or more resistor devices including a substrate, first and second electrically resistive materials, and an electrically insulating material between the first and second electrically resistive materials. The substrate includes a semiconductor material. A stepped trench is defined in the substrate by sidewalls and horizontal surfaces of the semiconductor material. The first electrically resistive material and the second electrically resistive material are within the stepped trench. A method of manufacturing a resistor device includes forming a stepped trench in the substrate, forming an etch stop material within the stepped trench, disposing an electrically resistive material within the stepped trench, disposing an electrically insulating material on the electrically resistive material, and repeating the disposing the electrically resistive material and the disposing the electrically insulating material operations a predetermined number of times.

Stacks of electrically resistive materials and related systems and apparatuses

Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features

Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

Memory device decoder configurations

Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells.

Dimension control for raised lines

Growing community of inventors

Boise, ID, United States of America

Ahmed Nayaz Noemaun