Analog Devices,inc.

Ahmed Mohamed Abdelatty Ali

Huseyin Dinc

Bryan Scott Puckett

Paritosh Bhoraskar

Gregory Wayne Patterson

Paridhi Gulati

Andrew Stacy Morgan

Scott Gregory Bardsley

Frank M Murden

Christopher Daniel Dillon

Ronald Bryce Gray, Iii

Michael Ray Elliott

Franklin Marshall Murden, Ii

Ravi Kishore Kummaraguntla

Ralph David Moore, Jr

Carroll Clifton Speir

James C Camp

Peter Delos

Joseph Michael Hensley

Aspects of the present disclosure include methods for operating discrete time circuits. A method in accordance with an aspect of the present disclosure may comprise sampling a first amplitude of a signal at a first time, sampling a second amplitude of the signal at a second time, comparing the first amplitude to the second amplitude, and adjusting a sampling time of the signal based at least in part on a difference between the first amplitude and the second amplitude.

Timing calibration techniques for discrete-time circuits

Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

Low power amplifier structures and calibrations for the low power amplifier structures

A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.

Track and hold circuits for high speed ADCS

Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

Background calibration of non-linearity of samplers and amplifiers in ADCs

Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

Background calibration of random chopping non-idealities in data converters

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Track and hold circuits for high speed and interleaved ADCs

A multi-input analog-to-digital converter (ADC), i.e., a single ADC, can receive multiple analog input signals and generate multiple digital outputs. To combine multiple analog input signals into a single multi-input ADC, the multi-input ADC would typically include multiple track and hold (T/H) circuits and an adder, which can consume a significant amount of power and incur large cost overhead. An improved approach is to combine multiple inputs through a unique T/H circuit in the front-end of the ADC. The multiple analog input signals can be aggregated using code sequences, without requiring a significant amount of external circuits.

Multi-input data converters using code modulation

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Low power high bandwidth high speed comparator

Background calibration techniques can effectively to correct for memory, kick-back, and order-dependent errors in interleaved switched-capacitor track-and-hold (T/H) circuits and amplifiers. The techniques calibrate for errors in both the track/sample phase and the hold-phase, and account for the effects of interleaving, buffer/amplifier sharing, incomplete resetting, incomplete settling, chopping, and randomization on the offset, gain, memory, and kick-back errors. Moreover, the techniques can account for order-dependent and state-dependent hold-phase non-linearities. By correcting for these errors, the proposed techniques improve the noise performance, linearity, gain/offset matching, frequency response (and bandwidth), and order-dependence errors. The techniques also help increase the speed (sample rate and bandwidth) and linearity of T/H circuits and amplifiers while simplifying the analog circuitry and clocking needed. These techniques comprehensively account for various memory, kick-back, and order-dependent effects in a unified framework.

Calibrating time-interleaved switched-capacitor track-and-hold circuits and amplifiers

One embodiment is an apparatus including a detector circuit electrically coupled between a signal source and a second circuit, the signal source generating a first signal, the detector circuit detecting a level of the first signal and generating a first control signal when the detected level of the first signal exceeds a first threshold value, and a clamping switch electrically coupled to receive the first control signal from the detector circuit, the clamping switch including a multi-terminal active device. The first control signal controls a state of the clamping switch such that the clamping switch clamps a level of a signal applied to the second circuit when the level of the first signal exceeds the first threshold value.

Signal level detection and overrange signal limiter and clamp for electronic circuits

Track and hold circuits for high speed and interleaved ADCS

Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

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Oak Ridge, NC, United States of America

Ahmed Mohamed Abdelatty Ali