Washington University

Ahmed Louri

Ke Wang

Hao Zheng

Jiajun Li

Yuechen Chen

We introduce SGCNAX, a scalable GCN accelerator architecture for the high-performance and energy-efficient acceleration of GCNs. Unlike prior GCN accelerators that either employ limited loop optimization techniques, or determine the design variables based on random sampling, we systematically explore the loop optimization techniques for GCN acceleration and provide a flexible GCN dataflow that adapts to different GCN configurations to achieve optimal efficiency. We further provide two hardware-based techniques to address the workload imbalance problem caused by the unbalanced distribution of zeros in GCNs. Specifically, SGCNAX exploits an outer-product-based computation architecture that mitigates the intra-PE (Processing Elements) workload imbalance, and employs a group-and-shuffle approach to mitigate the inter-PE workload imbalance.

SGCNAX: a scalable graph convolutional neural network accelerator with workload balancing

Systems and methods are disclosed for improving on-chip security, while minimizes the latency and cost of security techniques to improve system-level performance and power simultaneously. The framework uses machine learning algorithms, such as an artificial neural network (ANN), for runtime attack detection with higher accuracy. Further, a learning-based attack mitigation method using deep reinforcement learning is disclosed, where the method may be used to isolate the malicious components and to optimize network latency and energy-efficiency.

Systems and methods for learning-based high-performance, energy-efficient, and secure on-chip communication design framework

Systems and methods are disclosed for a centrosymmetric convolutional neural network (CSCNN), an algorithm/hardware co-design framework for CNN compression and acceleration that mitigates the effects of computational irregularity and effectively exploits computational reuse and sparsity for increased performance and energy efficiency.

Systems and methods for compression and acceleration of convolutional neural networks

A proactive fault-tolerant scheme which improves performance and energy efficiency for NoCs. The fault-tolerant scheme allows routers to switch among several different fault-tolerant operations. Each operation mode has different trade-offs among fault-tolerant capability, retransmission traffic, latency, and energy efficiency. Another example provides a proactive, dynamic control policy to balance and optimize the dynamic interactions and trade-offs. The example control policy uses example machine learning algorithm called reinforcement learning (RL). The example RL-based controller independently observes a set of NoC system parameters at runtime, and over time they evolve optimal per-router control policies. By automatically and optimally switching among the four fault-tolerant modes, the trained control policy results in minimizing system level network latency and maximizing energy efficiency while detecting and correcting errors.

Learning-based high-performance, energy-efficient, fault-tolerant on-chip communication design framework

With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase.

EZ-pass: an energy performance-efficient power-gating router architecture for scalable on-chip interconnect architecture

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

Interconnection network with adaptable router lines for chiplet-based manycore architecture

Systems and methods are disclosed for reducing latency and power consumption of on-chip movement through an approximate communication framework for network-on-chips ('NoCs'). The technology leverages the fact that big data applications (e.g., recognition, mining, and synthesis) can tolerate modest error and transfers data with the necessary accuracy, thereby improving the energy-efficiency and performance of multi-core processors.

Growing community of inventors

Vienna, VA, United States of America

Ahmed Louri