Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Ahmed Kari

Christophe Moreaux

David Naura

Pierre Rizzo

Olivier Tardieu

Michel Bardouillet

Orazio Musumeci

A passive contactless integrated circuit includes an electrically programmable non-volatile data memory (MEM), a charge accumulation booster circuit for supplying a high voltage necessary for writing data in the memory. The integrated circuit includes a volatile memory point for memorizing an indicator flag, and circuitry for modifying the value of the indicator flag when the high voltage reaches a critical threshold for the first time after activating the booster circuit.

Passive contactless integrated circuit comprising a flag for monitoring an erase/programming voltage

A method for configuring a memory space, the method including reading a piece of configuration information in the memory space, determining a division of at least one part of the memory space into memory banks according to the configuration information read; and allocating to each of the memory banks an access number to be used to access a data location in the memory bank, in combination with a logic address of the location in the memory bank.

Method for configuring a memory space divided into memory banks

A method for modulating the impedance of an antenna circuit supplying pump signals to a charge pump comprising at least one first pump stage and one last pump stage, the last pump stage supplying a continuous voltage. The output of the first pump stage is short-circuited by means of a switch and the last pump stage goes on pumping electric charges and supplying the continuous voltage. Application in particular to RFID passive transponders.

Antenna impedance modulation method

A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number of words in the block to be written, and controlling the memory to successively write each word in the memory during the write time.

Method for block writing in a memory

A method divides a number Nby a number which can be written in the form 2/k, n and k being whole numbers, and obtains a result N. The result Nis calculated by adding terms N*Ki/2for i ranging from 0 to N, the terms Ki being the constituent bits K, K, K, . . . Kof the number k expressed in binary. The method can be applied particularly to the production of a calibration circuit for calibrating a clock signal in a UHF transponder.

Method for dividing a number by a fraction having a number in the form of a power of 2 at the numerator

A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit.

Persistent volatile memory with sense amplifier and discharge switch

A method and device for generating a clock signal, the method including measuring, using a first clock signal, a characteristic of a reference event in a received signal, determining, using the first clock signal, a variation of a characteristic of a second event in a received signal, correcting the measurement according to the variation of the characteristic of the second event, and generating a second clock signal using the first clock signal according to the corrected measurement.

Method and device for generating a clock signal

A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.

Clock generation method and device for decoding from an asynchronous data signal

A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.

Binary frequency divider

A method checks the state of a set of memory cells of a memory having memory cells arranged in a memory array, row and column decoders for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive or non-conductive. The method includes features wherein all the memory cells of a set grouping together several memory cells are selected, and then simultaneously coupled to the sense amplifier, and the sense amplifier supplies a global state of all the selected memory cells to which it is coupled, if the latter are simultaneously non-conductive. Application is provided to the checking of a command for block-erasing a memory.

Method for checking block erasing of a memory and circuit thereof

A method for executing a write command for writing a binary word in a programmable memory, comprises writing each of the bits in a programmed state of a binary word to be written in a corresponding memory cell of the memory, reading each bit of the word written in the memory corresponding to a bit in the programmed state of the word to be written, comparing each bit in the programmed state of the word to be written with a corresponding bit read in the memory, and generating an error signal if at least one bit of the word to be written in the programmed state is different from the corresponding bit read. Application of the method can be particularly but not exclusively to integrated circuits for chip cards.

Method and device for checking the execution of a write command for writing in a memory

A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method includes the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the integrated circuit into service, storing, in the reference memory cells, bits of determined value forming an authorized combination of bits and, during the operation of the integrated circuit following its putting into service, reading and evaluating the reference memory cells and blocking the integrated circuit if the reference memory cells contain a forbidden combination of bits different from the authorized combination.

Integrated circuit with a data memory protected against UV erasure

A contactless integrated circuit receiving an RF signal comprises a clock-signal generator to produce a clock signal from a first half wave and a second half wave representing the received RF signal. Also disclosed is a method for the generation of a clock signal in which the first half wave and the second half wave are compared to produce the clock signal. The invention is adapated for use in contactless cards, transponders, and the like.

Integrated circuit comprising a clock-signal generator, smart card comprising an integrated circuit of this kind and associated method for the generation of clock signals

A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol

The invention concerns non-contact smart cards and, more particularly in such cards, a circuit for detecting data frames and providing them with a parallel format for their processing. The invention is characterised in that it consists in using the information contained in the first octets of the frame being currently received, thereby enabling to identify them as they are received and route them into registers (). This is provided by a state machine () whereof the shift from one state to the other is switched by the circuitry () output signals.

Growing community of inventors

Aix en Provence, France

Ahmed Kari