Intel Corporation

Ahmad Yasin

Michael W Chynoweth

Jason W Brandt

Ofer Levy

Rajshree Chabukswar

Angela D Schmid

Beeman C Strong

Stanislav Viktorovich Bratanov

Grant G Zhou

Eliezer Weissmann

Matthew C Merten

Seth Abraham

Andreas Kleen

Kimberly C Weier

Efraim Rotem

Joseph Nuzman

Igor Yanover

Jonathan D Combs

Liron Zur

Jared W Stark

Muhammad Taher

Raanan Sade

Mrittika Ganguli

Julius Yuli Mandelblat

Peggy J Irelan

Johan G Van De Groenendaal

Emile Ziedan

Charlie J Hewett

Ajay Amarsingh Singh

Doron Rajwan

Andrew J Herdrich

Eugene Gorbatov

Nir Rosenzweig

Russell Jerome Fenger

Lihu Rappoport

Jacob Doweck

Yoni Aizik

Chaim Shen-Orr

Baruch Chaikin

Reuven Elbaum

Israel Diamand

Ibrahim Hur

Monica Gupta

Yevgeni Sabin

Nir Misgav

Nir Tell

John M Esper

Jeffrey Baxter

Christopher Mark Chrulski

Asavari Paranjape

Moshe Cohen

Eti Pardo-Fridman

Joseph K Olivas

Omer Barak

Charlie Hewett

Patrick Konsor

Vidisha Chirra

Pavel Fridman

Michael Chynoweth

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

Code prefetch instruction

Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.

Methods, systems, and apparatuses for precise last branch record event logging

Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

Selective use of branch prediction hints

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

Apparatuses, methods, and systems toprecisely monitor memory store accesses

A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

Instruction and logic for tracking fetch performance bottlenecks

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

Precise longitudinal monitoring of memory operations

Embodiments are disclosed for monitoring processor performance, including cost of events. In an embodiment, a processor includes a first counter, a second counter, a handler circuit, and an enable circuit. The first counter is to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value. The second counter to measure a performance cost of the event. The handler circuit to generate and an event sampling record. The record is to include at least one value reflecting the performance cost. The enable circuit is to enable the handler circuit to generate the record.

Monitoring performance cost of events

Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Performance monitoring in heterogeneous systems

Apparatuses, methods, and systems to precisely monitor memory store accesses

An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

Apparatus and method for multithreading-aware performance monitoring events

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

The present disclosure is directed to systems and methods of detecting a side-channel attack detecting a translation lookaside buffer (TLB) miss on a virtual address lookup caused by the speculative execution of an instruction and determining that the physical memory address associated with the virtual address lookup contains a privileged object or a secret object. Range register circuitry determines whether the physical memory address is located in an address range containing privileged objects or secret objects. Performance monitoring counter (PMC) circuitry generates an interrupt in response to receipt of information indicative of the TLB miss and information indicative that the physical memory address contains a privileged object or a secret object. The PMC circuitry causes the storage of information associated with the speculatively executed instruction causing the virtual address lookup.

Active side-channel attack prevention

Growing community of inventors

Haifa, Israel

Ahmad Yasin