National Semiconductor Corporation

Texas Instruments Corporation

Ahmad Reza Bahai

Ali Kiaei

Ali Djabbari

Wei Ma

Reza Hoshyar

Nirmal Chindhu Warke

Gerard G Socci

Mounir Youssef Bohsali

Brian Lester Halla

Kevin Zheng

Xiang Gao

Bram Nauta

Haiyun Tang

Eric Klumperink

Masood Yousefi

Wenting Zhou

Karim Nassiri Toussi

Kumud Kumar Sanwal

Baher S Haroun

Peter Smeys

Visvamohan Yegnashankaran

Franco Maloberti

Ting-Ta Yen

Yunhong Li

Zhenyong Zhang

Jianhui Zhang

Karim Nassiri-Toussi

Mohammad Hadi Motieian Najar

Hamid Aghajan

Shougang Wang

Qingguo Liu

In one example, a semiconductor device includes an acoustic medium, a first transducer on the acoustic medium, a first electrode coupled to the first transducer, a second transducer on the acoustic medium, and a second electrode coupled to the second acoustic transducer. The semiconductor device also includes a semiconductor substrate to support the acoustic medium and first and second transducers. Mold compound encapsulates at least a portion of the acoustic medium, the first acoustic transducer, the second acoustic transducer, and the semiconductor substrate.

Acoustic isolator

Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number Ncycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

Fractional frequency clock divider with direct division

A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

CTLE gear shifting to enable CDR frequency lock in wired communication

A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The method includes, for a given IIR path for a received signal, updating gain of the given IIR path using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation; and updating a time constant of the given IIR path using a respective monitor tap error-data correlation with a second LMS update equation.

IIR DFE updating gain and time constants using LMS equations

A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Gear shifting from binary phase detector to PAM phase detector in CDR architecture

A method for controlling heat dissipated from a prosthetic retinal device is described. A heat transfer device employs the Peltier heat transfer effect to cool the surface of the retinal device that faces the retina by dissipating/transferring collected heat away from the retina and towards the iris or front of the eye. According to one embodiment, a heat pump is formed in a second substrate on the retinal device. The heat pump is controlled by a temperature sense device that activates the heat pump, when a first predetermined temperature limit is exceeded. The temperature sense device deactivates the heat pump, when a temperature of the retinal device drops below a second predetermined temperature. According to another embodiment, a supply current of the retinal device may pass through the heat pump and a direction of heat transfer by the heat pump can be reversed, when the first predetermined temperature is exceeded.

Heat transfer control for a prosthetic retinal device

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Sampling phase lock loop (PLL) with low power clock buffer

A system includes multiple speakers arranged in a speaker array configuration. The system also includes one or more filters configured to filter audio signals and generate filtered audio signals. The one or more filters are configured to operate using filter coefficients associated with a desired beam pattern to be produced by the multiple speakers. The system further includes at least one amplifier configured to amplify the filtered audio signals and provide the amplified filtered audio signals to the speakers. The one or more filters reside within or are coupled to the at least one amplifier. The system may further include a controller configured to modify at least one of the filter coefficients based on a change in the speaker configuration. The filters may operate independently of a centralized processor, and a centralized processor may not even be required to provide electronic beam forming.

Beam forming in spatialized audio sound systems using distributed array filters

Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Low power and low spur sampling PLL

Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Spur reduction technique for sampling PLL's

Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.

Sub-beam forming receiver circuitry for ultrasound system

A wireless sensor network for monitoring one or more selected environmental characteristics. Multiple wireless signal transceivers, disposed in respective portions of a selected environment, respond to one or more wireless beacon signals by selectively collecting, processing and storing data corresponding to one or more characteristics of such portions of the selected environment, and by selectively transmitting respective wireless response signals containing selected portions of such data. Alternatively, multiple wireless signal transceivers, disposed in respective sub-networks in portions of a selected environment, collect and convey data corresponding to one or more characteristics of such selected environment portions.

Wireless sensor network for monitoring one or more selected environmental characteristics

A cellular telephone handset utilizes an electrically-steered directional antenna to increase the received signal strength when the handset is in a poor signal environment. As a result, the handset reduces the need for an end user to tilt and twirl their head to try and find the direction of the strongest signal strength.

Cellular telephone handset with increased reception sensitivity and reduced transmit power levels

Voltage conversion and charging circuitry and method for converting an alternating current (AC) voltage to a direct current (DC) voltage for charging an energy storage element (e.g., battery or supercapacitor). An output capacitance, which is initially charged quickly for use in the slower charging of a battery, also maintains the charge on an input capacitance which provides power for the charging control circuitry during such charging process. In accordance with a preferred embodiment, the DC charging current is substantially constant during a first time interval following which the DC charging power is substantially constant during a second time interval.

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Lafayette, CA, United States of America

Ahmad Reza Bahai