Nvidia Corporation

Ahmad Itani

Ravi P Singh

Jagadeesh Sankaran

Yen-Te Shih

Ching-Yu Hung

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Using a hardware sequencer in a direct memory access system of a system on a chip

Performing load and permute with a single instruction in a system on a chip

Performing load and store operations of 2D arrays in a single cycle in a system on a chip

Using per memory bank load caches for reducing power use in a system on a chip

Built-in self-test for a programmable vision accelerator of a system on a chip

In various examples, systems and methods for reducing written requirements in a system on chip (SoC) are described herein. For instance, a total number of iterations may be determined for processing data, such as data representing an array. In some circumstances, a set of iterations may include a first number of iterations that is less than a second number of iterations. As such, and during execution of the set of iterations, a predicate flag corresponding to an excess iteration of the set of iterations may be generated, where the excess iteration corresponds to an iteration that is part of a number of excess iterations that is associated with a difference between the first number of iterations and the second number of iterations. Based on the predicate flag, one or more first values corresponding to the iteration may be prevented from being written to memory.

Reduced memory write requirements in a system on a chip using automatic store predication

Hardware accelerated anomaly detection using a min/max collector in a system on a chip

Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip

Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip

Performing multiple point table lookups in a single cycle in a system on chip

A VPU and associated components include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators are used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer is included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU executes a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

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San Jose, CA, United States of America

Ahmad Itani