Cypress Semiconductor Corporation

Ahmad Chatila

Kuantai Yeh

James Montague Cleeves

Bo Jin

Roger F Caldwell

Shahin Sharifzadeh

Kaichiu Wong

Daniel J Arnzen

A semiconductor device memory cell () can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell () can include a first inverter () and second inverter () arranged in a cross-coupled configuration. A capacitor () can be coupled between a first storage node () and second storage node (). A capacitor () can be a 'built-in' capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

Soft error resistant memory cell and method of manufacture

The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Thin liner layer providing reduced via resistance

The present invention concerns a process that maintains a second (or 'replica') set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or 'replica') alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be 'printed' in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an 'open frame' process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

Alignment process compatible with chemical mechanical polishing

Growing community of inventors

Santa Clara, CA, United States of America

Ahmad Chatila