Maxim Integrated Products, Inc.

Fairchild Semiconductor Corporation

Nova Semiconductor, Inc.

D2a Audio LLC

Ahmad Ashrafzadeh

Chung-Lin Wu

Maria Cristina Estacio

Viren V Khandekar

Karthik Thambidurai

Daniel Marvin Kinzer

Oseob Jeon

Janusz Bryzek

Amit Subhash Kelkar

Etan Shacham

Maria Clemens Ypil Quinones

Justin N Chiang

John R Constantino

Timwah Luk

Hien D Nguyen

Vijay Ullal

Robert L Krause

Michael M Dube

Adrian Mikolajczak

Viresh Patel

Mansour Izadinia

Nitin Kalje

Ignacio McQuirk

A method for measuring electrical quantities in an electrical system includes obtaining a first set of known electrical outputs of an electrical quantity sensor at a first temperature. The method also includes obtaining a second set of known electrical outputs of the electrical quantity sensor at a second temperature that is different from the first temperature. The method further includes measuring an operational temperature of one or more locations in the electrical system. The method still further includes computing a pair of reference electrical output values corresponding to the measured operational temperature in accordance with the first set of known electrical outputs at the first temperature and the second set of known electrical outputs at the second temperature. The method also includes interpolating among the pair of computed reference electrical output values to determine a temperature-corrected electrical quantity based on the measured operational temperature and the reference electrical output values.

Methods and systems for managing multi-cell batteries

A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital convertors for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.

A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital converters for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Isolation between semiconductor components

Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.

Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer

Disclosed are stereo sound system devices and methods for reproducing stereo sound with improved auditory experience and reduced speaker rattle. In some embodiments, the disclosed arrangement of speakers on the sound system housing and driving low frequency speakers with the same signal contribute to the improved auditory experience and reduced speaker rattle effect.

Methods and devices for reproducing stereo audio

In a general aspect, an apparatus can include a temperature measurement circuit configured to produce a first signal indicating a first operating temperature of a first semiconductor device and a temperature comparison circuit operationally coupled with the temperature measurement circuit. The temperature comparison circuit can be configured to compare the first signal with a second signal indicating a second operating temperature of at least a second semiconductor device and produce a comparison signal indicating whether the indicated first operating temperature is higher, lower or equal to the indicated second operating temperature. The apparatus can also include an adjustment circuit configured to adjust operation of the first semiconductor device based on the comparison signal.

Load balancing in discrete devices

In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.

Packaged semiconductor devices and methods of manufacturing

In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Package including a semiconductor die and a capacitive component

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Technique for wafer-level processing of QFN packages

Communication methods and apparatus and power supply controllers using the same. The method includes transferring information over a line from a first location to a second location as a voltage signal while simultaneously transferring information over the same line from the second location to the first location as a current signal. Further, digital information may be transmitted over the same line. When applied to a power supply controller system, a master controller may control a plurality of slave controllers by initially setting up the slave controllers by transmitting digital information to the slave controllers, and then maintaining a set point for each controller while monitoring controller characteristics over the same lines.

Communication methods and apparatus and power supply controllers using the same

Apparatus related to an improved package including a semiconductor die

Techniques for wafer-level processing of QFN packages

Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.

Growing community of inventors

Morgan Hill, CA, United States of America

Ahmad Ashrafzadeh