Texas Instruments Corporation

Ah-Lyan Yee

Sharat C Prasad

Martin J Izzard

James D Gallia

Randall J Landry

Pak Kuen Fung

E Ajith Amerasekepa

A programmable fast packet switch testbed (,) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The programmable switch (,) is arranged as an add-on peripheral to a conventional computer system including a host central processing unit (CPU) (,). The switch (,) includes a plurality of port processors (,) in communication with port interfaces (,); each of the port interfaces (,) is a conventional interface for high data rate communication, while the port processors (,) are programmable logic devices. The switch fabric is realized in a multiple slice fashion, by multiple programmable logic devices (,). A central arbiter (,), also realized in programmable logic, controls routing of cells within the switch (,). Programming of the port processors (,), fabric slices (,), and arbiter (,) is effected by downloading, into these devices, bit-streams supplied by the host CPU (,) that define the switch architecture, including selection of input or output queuing and the fabric type, along with the implementation of traffic management algorithms in the port processors (,), fabric slices (,), and arbiter (,). Each of the port processors (,), fabric slices (,), and arbiter (,) also contain memory locations for storing results of operation, which are read by the management port (,) over a management bus (COMET), and may then be forwarded to the host CPU (,), without interfering with switch traffic. The programmable switch (,) is therefore capable of full speed operation as a fast packet switch, thus providing accurate evaluation results.

Programmable architecture fast packet switch

An output driver device (,) includes a first output transistor (,) and a second output transistor (,) coupled to a bias transistor (,). The bias transistor (,) is coupled to a ground potential. The first output transistor (,) is coupled to a first output pad (,) and the second output transistor (,) is coupled to a second output pad (,). The output driver device (,) has a direct non-metal path to ground potential from either the first output pad (,) or the second output pad (,). In this manner, an electrostatic discharge device on either the first output pad (,) or the second output pad (,) can be absorbed through the first output transistor (,) or the second output transistor (,), respectively, and through the bias transistor (,) without damaging the output driver device (,).

Output driver device with electrostatic discharge protection

A BiCMOS gate array base is disclosed which is capable of simultaneously implementing a BiCMOS gate and/or a multitude of CMOS gates. The cell has symmetry about 1 axis, with the bipolar devices in the center and equally accessible for interconnect by two CMOS sections. The cell allows half-cell macro circuit blocks to be placed into the base cell in an independent and flexible fashion. The same macro can be placed in either CMOS section because of the mirror symmetry. The base cell can be divided into 2 units of macro placement. The number of devices in the CMOS section is variable. This cell architecture can be extended to other mixed technologies.

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Ah-Lyan Yee