Synopsys, Inc.

Virage Logic Corporation

Agustinus Sutandi

Yanyi Liu Wong

Todd E Humes

Chad A Lindhorst

Alex May

Martin L Niset

Troy Nathan Gilliland

Rebecca Shiu Yun Cheng

Vikramaditya Kundur

Ross Peterson

Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.

Memory power supply load management

A memory system with improved power consumption and operation speed. A memory system performs a data read operation in a low power read mode to improve operation speed and reduce power consumption by biasing bit cells in the memory system at a negative voltage. The use of the negative voltage minimizes changing of voltages of the bit cells. Additionally, the memory system performs data read operation in a margin read mode to improve accuracy of the reading by biasing the bit cells at a positive voltage.

Non-volatile memory with negative bias

Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node.

High voltage generation system and method employing a charge pump and producing discrete voltage values

Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

High-voltage switch using three FETs

A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.

Current source with low power consumption and reduced on-chip area occupancy

High-voltage switch using three FETS

Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

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Issaquah, WA, United States of America

Agustinus Sutandi