Broadcom Corporation

Adaptec, Inc.

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Newport Communications, Inc.

Afshin Momtaz

Jun Cao

Namik Kocaman

Armond Hairapetian

Delong Cui

Ali Nazemi

Mario Caresosa

Vivek Telang

David Chung

Chung-Jue Chen

Xin Wang

Anand Jitendra Vasani

Adesh Garg

Mahmoud Reza Ahmadi

Siavash Fallahi

Tamer Mohammed Ali

Vasudevan Parthasarathy

Bharath Raghavan

David Kyong-Sik Chung

Burak Catli

Ali Ghiasi

Heng Zhang

Mehdi Khanpour

Hassan Maarefi

Hong Chen

Thomas J Kolze

Bruce Joseph Currivan

Sudeep Bhoja

Bo Zhang

Guangming Yin

Davide Tonietto

Magesh Valliappan

Jiawen Zhang

Mahyar Kargar

Kun Chuai

Ichiro Fujimori

Kang Xiao

Michael M Green

Velu Pillai

Ullas Singh

Rajesh Satapathy

Sundararajan Chidambara

Chang Liu

Hyo Gyuem Rhew

Vasudevan Parthasarthy

Wee-Guan Tan

Kangmin Hu

Mohammed Abdul-Latif

Kuo-J Huang

Pang-Cheng Hsu

Ramon Alejandro Gomez

Kambiz Vakilian

Jay Proano

Lorenzo Longo

Meisam Honarvar Nazari

Henry Arnold Park

Iuri Mehr

Ramy Awad

Arvindh Iyer

Seong-Ho Lee

German Gutierrez

Alireza Nilchi

Michael Furlong

Germain Gutierrez

Wayne Wah-Yuen Wong

Mario T Caresosa

Mohammad S Nejad

Hongtao Jiang

Amr Amin Hafez Amin Abou-El-Sonoun

Vikram Natarajan

Kuo-J (Nick) Huang

Randy Stolaruk

Ahmadi Mahmoud

Maarefi Hassan

Natarajan Vikram

An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.

Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

Synchronization of devices with a gapped reference clock

Disclosed herein are related to systems and methods for providing different power supply levels. In one aspect, a first circuit generates a first signal having a first amplitude according to a first supply voltage. A latch may be coupled to a resistor of a plurality of resistors coupled in series. One end of the resistor may be configured to provide to the latch a second supply voltage higher than the first supply voltage according to a third supply voltage higher than the second supply voltage, and another end of the resistor may be configured to receive the third supply voltage. The latch may modify the first signal to provide a second signal, according to the second supply voltage. An amplifier may amplify the second signal to provide a third signal having a second amplitude larger than the first amplitude, according to the third supply voltage.

Power supply generation for transmitter

A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.

Pre-driver peaking technique for high-speed DACs

A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Multilane serdes clock and data skew alignment for multi-standard support

An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.

Increasing output amplitude of a voltage-mode driver in a low supply voltage technology

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

High-speed, low-power reconfigurable voltage-mode DAC-driver

A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Phase alignment architecture for ultra high-speed data path

A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Low-power high swing CML driver with independent common-mode and swing control

Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Transceiver including a high latency communication channel and a low latency communication channel

Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

Reference-less voltage controlled oscillator (VCO) calibration

A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes

A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

Resonant clock amplifier with a digitally tunable delay

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Laguna Hills, CA, United States of America

Afshin Momtaz