Axiom Microdevices, Inc.

Marvell Asia Pte., Ltd.

Broadcom Corporation

Other

Afshin Mellati

Frank Carr

Seyed Ali Hajimiri

Florian Bohn

Scott D Kee

Ichiro Aoki

Hui Wu

Alexandre Rudolph Kral

Donald McClymont

Rahul Magoon

Cindra Abidin

Liang Fan

Espen Olsen

Quanli Lu

Lawrence M Burns

Chun-Ying Chen

Robert G Wiley

Myles H Wakayama

Young J Shin

James Y C Chang

David S P Ho

Iconomos A Koullias

Dana Vincent Laub

Fazil Ahmad

Hsiang-Bin Lee

Pera Florin

Patrick Pai

Rabul Magoon

Luke Thomas Steigerwald

Ron Lipka

Alexander Kral

Linghsiao Wang

Amr M Fahim

Stephen A Jantzi

Donald McGlymont

Seyed-Ali Hajimiri

Alexandre Kral

Donald Mcclymont

David SP Ho

James YC Chang

Young Joon Shin

A first network device includes a pair of clock tree circuits, a feedback path, and a transceiver. The pair of clock tree circuits is configured to generate output clock signals, which are complementary to each other. The feedback path includes a skew detection circuit and a gain amplifier. The skew detection circuit detects a skew in the output clock signals and generates a pair of voltage signals based on a voltage-to-current and a current-to-voltage conversion of the output clock signals. The pair of voltage signals is indicative of the skew between the output clock signals. The gain amplifier amplifies the pair of voltage signals and, based on the amplified pair of voltage signals, adjusts respective delays in the output clock signals. The transceiver, based on the output clock signals, controls transfer of data to or from a second network device that is separate from the first network device.

Skew detection and correction of complementary clock signals

A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.

Low power time-interleaving DAC with pseudo interleaved architecture

A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an 'ON' state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.

Time-interleaved current-based digital-to-analog converter (current DAC)

A method for dynamically calibrating a time-interleaved digital-to-analog converter (DAC) includes receiving a digital input signal, generating, from the digital input signal, an output analog signal using DAC circuitry, generating, from the digital input signal, a model analog signal using DAC modeling circuitry, adjusting a digital model based on the model analog signal and the digital input signal, determining at least one of an offset error and a gain error based on comparing the output analog signal to the model analog signal, and generating an error correction signal based on the at least one of an offset error and a gain error.

Method for adaptive calibration of a digital-to-analog converter (DAC)

An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Multi-primary distributed active transformer amplifier power supply and control

A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

Accurate radio frequency filtering using active intermediate frequency feedback

A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Integrated direct conversion satellite tuner

Supply circuit for power amplifier drivers

Growing community of inventors

Laguna Niguel, CA, United States of America

Afshin Mellati