Intel Corporation

Ady Tal

Ron Gabor

Tomer Stark

Joseph Nuzman

Ali-Reza Adl-Tabatabai

Bratin Saha

Yang Ni

Jeffrey V Olivier

Sion Berkowits

James Henry Cownie

Moshe Maury Bach

Raanan Sade

Ravi Rajwar

Karthik Raman

Alex Gerber

Roman Dementiev

Adam Welc

Adam Wele

Ariel Slonim

Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.

Device, system and method to detect an uninitialized memory read

Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.

Heap management for memory corruption detection

Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.

Memory write protection for memory corruption detection architectures

An apparatus and method are described for floating point operation (FLOP) accounting. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch instructions from system memory, the instructions including at least one masked vector floating point instruction to perform operations on a plurality of floating point data elements; a mask register to store a mask value associated with the masked vector floating point instruction; a decoder to decode the masked vector floating point instruction; and floating point operations (FLOP) accounting circuitry to read the mask register to determine a number of floating point operations to be performed during execution of the masked vector floating point instruction.

Apparatus and method for instruction-based flop accounting

Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

Suspendable load address tracking inside transactions

Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.

Byte level granularity buffer overflow detection for memory corruption detection architectures

Memory corruption detection technologies are described. A method can include receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object. The method can further include allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested. The method can further include writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks. The method can further include creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object. The method can further include sending, to the application, the pointer.

Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.

Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

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Zichron Yaacove, Israel

Ady Tal