Koninklijke Philips Corporation N.v.

Nxp B.v.

Adrianus Marinus Gerardus Peeters

Jozef Laurentius Wilhelmus Kessels

Mark Nadim Olivier De Clercq

Cornelis Hermanus Van Berkel

Markus Feuser

Patrick Willem Hubert Heuts

Paul Wielage

Daniel Timmermans

Suk Jin Kim

Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.

Pipeline synchronisation device

The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed. DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available. The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply. As a result the processes in the self-timed logic take place in an unpredictable way and current consumption becomes affected by severe noise and DPA cannot be successfully applied.

Method and arrangement for increasing the security of circuits against unauthorized access

An electronic circuit that includes components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.

Electronic circuit with asynchronously operating components

An electronic circuit is provided that comprises a plurality of storage elements (-) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Controlling power consumption peaks in electronic circuits

A chain of processing element () with a logic circuit () and a storage element () is provided. The storage elements () of all except a final processing element () in the chain have one or more outputs coupled to the logic () of a next processing element () in the chain. A timing circuit () controls respective loading time points at which the storage elements () load data from the logic circuits () in respective ones of the processing elements (). The data is loaded progressively later in processing elements () that successively precede one another in the chain. The time interval between successive loading time points of the final processing element () includes loading time points of loading all processing elements () other than the final processing element ().

Electronic circuit with a chain of processing elements

A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.

Information exchange between locally synchronous circuits

An integrated circuit according to the invention comprises at least a first and a second circuit ( resp.) and a first and a second signal path ( and resp.) between the first and the second circuit. The first and the second signal path each comprise a selection element ( ) which has a first input ( ) coupled to the first circuit ( ), and a second input ( ). The selection element ( ) has an output (30 ) coupled to the second circuit ( ). The second input ( ) of the selection element ( ) of the second signal path ( ) is coupled to a memory element ( ). The output ( ) of the selection element ( ) of the first signal path ( ) is coupled to an input ( ) of the memory element ( ).

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Eindhoven, Netherlands

Adrianus Marinus Gerardus Peeters