Silicon Laboratories Inc.

Adrianus Josephus Bink

Paul Zavalney

Brian Taylor Brunn

Thomas Saroshan David

Ricky Setiawan

Pio Balmelli

Daniel J Cooley

Chester Yu

Joshua Jay Norem

Wajid Hassan Minhass

Rejoy Roy Mathews

Aslam Rafi

In one embodiment, an apparatus includes: a fabric circuit to couple between a plurality of managers and a memory; and multi-bank memory control circuitry coupled to the fabric circuit and to couple to a plurality of banks of the memory and including a plurality of first ports to receive memory requests from the plurality of managers, The multi-bank memory control circuitry is to enable each of the plurality of managers to access the memory in parallel. A global monitor is coupled to the multi-bank memory control circuitry and includes a plurality of second ports and a plurality of state machines, each of the plurality of state machines to be associated with one of the plurality of managers. Each of the plurality of state machines is configured to enforce exclusivity of a memory region on behalf of a manager and concurrently enable non-exclusive access to the memory region.

Global monitor for multi-port memory controller

An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

External nonvolatile memory with additional functionality

An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

Integrated circuit clock management during low power operations

In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

System, apparatus and method for flexible control of a voltage regulator of an integrated circuit

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Oslo, Norway

Adrianus Josephus Bink