Koninklijke Philips Corporation N.v.

Nxp B.v.

Adrianus Josephus Bink

Jan Hoogerbrugge

Jeroen Anton Johan Leijten

Marco Jan Gerrit Bekooij

Johan Sebastiaan Henri Van Gageldonk

Bart Mesman

Mark Nadim Olivier De Clercq

Paul Stravers

Bernardo De Oliveira Kastrup Pereira

Cornelis Arnoldus Josephus Van Eijk

Mark N O De Clercq

An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

Intergrated circuit and a method of cache remapping

A data processing circuit contains a register file () with a write port and a pipeline of instruction processing stages (-). A timing circuit () is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages () are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned () requires writing. A write sequencing circuit () performs write tests alternately for instruction dependent information in the first and second one of the stages (). When the write sequencing circuit () performs the write test for a particular one of the stages (), it tests whether the instruction dependent information in the particular one of the stages () requires writing of a result. If so, the write sequencing circuit (), delays transfer of new instruction dependent information through the pipeline (-) to the particular one of the stages () until the write port has been committed to writing the result before any results that the write port is subsequently committed to write.

Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering

An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a test mode in which the latch is held open.

Electronic circuit

The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.

Interruptible digital signal processor having two instruction sets

A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected based on a corresponding indication in said instruction word and the register address is supplied to said selected register files. Result values can be broadcasted to multiple registers in a single processor cycle while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Signal processing device and method for supplying a signal processing result to a plurality of registers

The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF, ALU, L/S, BU) of the architecture, whereas the complete instruction set covers the entire architecture (RF, UC, UCRFUCUCRFUCUCRFUC). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.

Retargetable compiling system and method

A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction. A respective configuration program is generated for each combination of instructions. Each time when an instruction from one of the combinations is needed during execution and the configurable functional unit is not configured with the configuration program for that combination, the configuration program for all of the instructions of that combination into the configurable functional unit. The reconfigurable instruction selects which instruction of the combination is executed.

System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time

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Eindhoven, Netherlands

Adrianus Josephus Bink