Koninklijke Philips Corporation N.V.

Dalsa Corporation

Teledyne Dalsa B.v.

Adrianus Johannes Mierop

Willem Hendrik Maes

Daniel Wilhelmus Elisabeth Verbugt

Alouisius Wilhelmus Marinus Korthout

Anton Petrus Maria Van Arendonk

Edwin Roks

Matthias Sonder

Willem Johan De Haan

Johannes H Huijsing

Martijn F Snoeij

Albert J P Theuwissen

A method of scanning pixels, each pixel including a photodiode and a sense node formed in the substrate, including a transfer gate coupled between the photodiode and the sense node, and including a memory gate coupled between the photodiode and the transfer gate. The method switches a control signal, connected to a memory gate electrode of all pixels, alternately between a first voltage and a second voltage that is intermediate between the first voltage and a substrate voltage. The first voltage transfers all photo charge in each photodiode into the respective memory gate. The second voltage both (1) holds all photo charge already transferred into the memory gate and (2) blocks further transfer of photo charges into each memory gate. The method further includes reading out photo charge from the memory gate on a row-by-row basis while the control signal is at the second voltage.

Pixel for correlated double sampling with global shutter

A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.

Single slope analog-to-digital converter

The invention relates to a semiconductor device with a semiconductor body comprising a CMOS image sensor with an active region having viewed in projection first sides and second sides perpendicular to the first sides said active region comprising a matrix of active pixels arranged in rows and columns, each pixel having a photosensitive region, the device further comprising a plurality of circuit elements for operating the pixel in the image forming process, the plurality of circuit elements comprising a first set of circuit elements for read-out of the columns and a second set of circuit elements for controlling the rows. According to the invention a first part of the plurality of circuit elements is positioned outside the matrix along one of the first sides and a second part of the plurality of circuit elements is positioned within the matrix of active pixels remote from the second sides. Preferably the first part elements comprises the read-out circuitry of the columns and the second part elements comprises the control circuitry of the rows, the latter preferably being distributed over a number of centrally positioned columns. A device according to the present invention is very suitable for X-ray medical imaging.

Semiconductor device with a CMOS image sensor, apparatus comprising such a semiconductor device and method of manufacturing such a device

An array-based C-MOS sensor device is provided with a facility for on the basis of non-destructive cell readout generating a radiation dose-sensing signal. In particular, the facility is arranged for accessing a subset of multiple distributed C-MOS cells across the array and feeding by such accessed cells an algorithmic means for therein generating an overall feedback dose control signalization and/or an over-all trigger signalization.

C-MOS sensor readout from multiple cells across the array to generate dose sensing signal

The invention relates to a method of manufacturing an integrated circuit () on a die (), wherein the die () forms a detachable part of a wafer () comprising a plurality of dies that are separated from each other by dicing lanes (). The method comprises a step of applying a metallization pattern () in at least one of the dicing lanes () to form a communication bus comprising at least one communication bus circuit () that is part of the integrated circuit (). Said step is followed by a step wherein the integrated circuit () is tested according to a predetermined testing method which uses the communication bus circuit () to communicate with the integrated circuit (). This step is followed by a next step wherein the die () is detached from the wafer (). The communication bus circuit () is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (), it communicates in the wafer test mode. The invention also relates to an integrated circuit () obtained by means of the manufacturing method, a wafer () comprising an integrated circuit () obtained by means of the manufacturing method, and a system comprising an integrated circuit () obtained by means of the manufacturing method.

METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT OBTAINED IN ACCORDANCE WITH SAID METHOD, WAFER PROVIDED WITH AN INTEGRATED CIRCUIT OBTAINED IN ACCORDANCE WITH THE METHOD, AND SYSTEM COMPRISING AN INTEGRATED CIRCUIT OBTAINED BY MEANS OF THE METHOD

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Eindhoven, Netherlands

Adrianus Johannes Mierop