Cadence Design Systems, Inc.

Adriana Cassia Rossi De Almeida Braz

Georgia Penido Safe

Chung-Wah Norris Ip

Vincent Gregory Reynolds

Guilherme Henrique De Sousa Santos

Abner Luis Panho Marciano

Raquel Lara Dos Santos Pereira

Laiz Lipiainen Santos

Rodrigo Fonseca Rocha Soares

Guilherme Seminotti Braga

Julio Alexandre Silva Rezende

Hudson Dyele Oliveira

Caio Texeira Campos

Breno Rodrigues Guimares

Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.

Partition-based circuit analysis and verification

Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.

Methods, systems, and computer program product for connectivity verification of electronic designs

Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.

Methods, systems, and computer program product for verifying an electronic design

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Brasilia, Brazil

Adriana Cassia Rossi De Almeida Braz