International Business Machines Corporation

Globalfoundries Inc.

Globalfoundrles Inc.

Adrian Stephen Butter

James P Kuruts

Agnes Yee Ngai

Chang Y Kao

Kai Yang

John Mark Kaczmarczyk

Bin Sun

Robert J Yagley

Bin Yu

Liang Chen

Michael Anthony Sorna

Eric M Foster

Glenn David Gilda

Sivarama K Kodukula

Charles E Boice

Yiftach Benjamini

Thomas B Mathias

Edward Francis Westermann

Ronald S Svec

Liang Ge

Charles John Stein

Robert L Woodard

Jilei Yin

Leonard R Chieco

Nader Mohsenian

Hugh C Holland

Yijian Qi

Howard E Parsons

Chang-Yung Kao

Brian S Finkel

Gary A Zisko

A system and apparatus for obtaining clock synchronization of networked devices and related method are provided. Embodiments include a computer-implemented system, including a primary device having a first high accuracy timestamping assist (HATA) unit attached to a first physical layer; a first time stamping unit; a first clock control; a first medium access control layer connected to the first time stamping unit and the first physical layer via a medium independent interface. A secondary device includes a second HATA unit attached to a second physical layer; a second timestamping unit; a second clock control. The first and second HATA units are configured to detect a departure time, an arrival time, or a combination thereof of a first alignment marker over transmitter serializer and receiver deserializer interfaces of a data transmission between the primary device and the secondary device.

Nanosecond accuracy of timestamping by leveraging alignment marker and method for producing the same

In methods, systems, and devices, master and slave node timestamp synchronization units identify a node start frame delimiter of a time protocol message on transmission medium by matching patterns in the time protocol message to known start frame delimiter patterns. Master and slave node processors of such timestamp synchronization units capture a corresponding node clock time at which the node start frame delimiter is identified by referring to a corresponding node clock signal while each is identifying the node start frame delimiter. The master and slave node processors perform compensation of the node clock time by making adjustments to the node clock time for known time latency. The master and slave node timestamp synchronization units then output the node clock time as timestamps to corresponding timestamp units.

Nanosecond accuracy under precision time protocol for ethernet by using high accuracy timestamp assist device

In high-speed link structures a receiver outputs a signal detect indicator (SDI) with a first logic value when transmissions are detected and a second logic value when suspension of transmissions is detected. A controller detects transitions in the SDI and causes corresponding transitions in an energy detect indicator (EDI). A physical control sublayer (PCS) has different operating states that cause the receiver to operate in different power modes and transitions between the operating states based on the EDI. If the EDI has the second logic value, the PCS remains in a non-active state and the receiver operates in a low power idle (LPI) mode. When the EDI transitions to the first logic value, the PCS exits the non-active state and the receiver operates in a non-LPI mode. To ensure that the PCS properly enters and doesn't pre-maturely exit the non-active state, EDI transitions to the first logic value are delayed.

Energy efficient high-speed link and method to maximize energy savings on the energy efficient high-speed link

Techniques for forward error correction synchronization are described herein. The techniques include receiving a bit stream over a transmission link and determining a starting location of a first code word within the bit stream. Determining the starting location of the first code word includes identifying an error correction block associated with a previously received second code word, and designating a bit subsequent to the error correction block as the starting location of the first code word.

Forward error correction synchronization

A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

Programmable direct memory access controller having pipelined and sequentially connected stages

Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Access table lookup for bus bridge

A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine.

Scheduler design to optimize system performance using configurable acceleration engines

Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

Efficient, flexible motion estimation architecture for real time MPEG2 compliant encoding

Method, system and computer program product are provided for adaptively encoding in hardware, software or a combination thereof a sequence of video frames in real-time. Pre-encode perceptual activity measurement processing is employed to derive statistics on each frame of the sequence of video frames to be encoded. The statistics are used by variable bit rate logic to obtain a number of bits to be used in encoding each frame. The number of bits to be used is provided to a single encoding engine, which encodes the sequence of video frames and produces a constant quality, variable bit rate bitstream output. The pre-encode processing employs a regulator as the global data flow control and synchronization for the encoder. Perceptual activity analysis on each frame of the sequence of video frames can derive information on, for example, shading, scene change, fade, color, motion and/or edge presence within the frame. Voting gives greater weight to the presence of certain characteristics within the frame.

Real-time variable bit rate encoding of video sequence employing

A method of and apparatus for identifying a Dual Prime motion estimation best match and generating motion vectors pertaining thereto for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The Dual Prime method of motion estimation described herein includes a method of generating motion vectors. The motion vectors point from a macroblock in a current field to a macroblock in a past field for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The first step in the method is defining a macroblock in a parity field of the current picture. Next, the preceding field of the same or opposite parity is searched to find a first best match macroblock in the preceding field. Once a best match macroblock is found, a vector is formed from the current macroblock in the current parity field to the first best match macroblock in the preceding parity field. This vector is scaled so that it refers to a second dual prime macroblock in the opposite parity field, that is the parity field of opposite parity with respect to the first best match macroblock which defines the center of a dual prime search window. Then, the average of the first best match macroblock and the set of second dual prime macroblocks in the dual prime search window is taken and the search window is searched to determine the best match dual prime macroblock. The search is typically conducted at half pixel locations inside a one square pixel dual prime search window. The appropriate dual prime motion vector and differential motion vector (dmv) are formed. These are motion vectors which point to both the first best match macroblock and the best match dual prime macroblock.

Dual prime motion estimation system and method

A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously. The serial bit stream and digital strobe signal are asynchronous relative to the clock. Hardware logic determines when contents of the third register is same as contents of the second register; this indicates termination of the serial bit stream and digital strobe signal.

Apparatus and method for detecting end of serial bit stream

A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers. A third clock triggers the fifth and sixth registers simultaneously to latch bits 0 and 2, respectively, of a series of four bits. A fourth clock triggers the seventh and eight registers simultaneously to latch bits 1 and 3, respectively, of the series of four bits.

High speed asynchronous serial to parallel data converter

A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

Scalable MPEG2 compliant video encoder

A system and method for implementing a new protocol that uses new data structures in order to improve the performance of a token ring without changing its topology or degrading its fairness. A primary sender sends a data frame containing a data field addressed to a primary receiver. The protocol allows the primary receiver to enter 'transmit mode' and assume another role as a secondary sender when the data frame is received and copied. The secondary sender overwrites the data field. Then, the secondary sender designates a secondary receiver to receive the update data and sends an acknowledgement message back to the primary sender to indicate that it has received data. The secondary receiver sends an acknowledgement to the secondary sender when the secondary transmission data is received. The primary sender checks for an acknowledgement from the primary receiver when the data frame returns. Then the primary sender transmits the data frame downstream. The primary sender regenerates a token and either releases it or seizes it based on whether it has more data to send. The secondary sender verifies the acknowledgement from the secondary receiver and returns to 'listen mode'.

Method and system for improving the performance of a token ring network

A method and system for increasing performance on a standard dual ring token ring by generating one or more sub-tokens so that multiple data transmissions can occur concurrently. Upon receipt of a data frame from the token holder, interface logic enables a receiver to generate a sub-token frame. The sub-token is used to notify the next downstream station that it may transmit data frames to other downstream stations. In this way, a second data transmission path can be established between downstream stations. In a similar manner, the receiver of a data frame sent by a sub-token owner will generate a sub-token frame for use by the next downstream station when its data arrives. Each sub-token is used to create a new sub-ring, thus allowing for concurrent data transmissions. Each new sub-ring must obey token ring protocol to avoid data collisions.

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Binghamton, NY, United States of America

Adrian Stephen Butter