Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Global Unlimited Company

Adrian Sherry

Damien Joseph McCartney

Michael Byrne

Colin Gerard Lyden

Gabriel Banarie

Tomas Tansley

Claire Croke

Aine McCarthy

Mary McCarthy

Dan O'Donovan

Sean Wilson

Giovanni C Dotta

Fiona Treacy

Roberto S Maurino

Thomas J Meany

Bhargav R Vyas

Andreas Callanan

Arvind Madan

Michal Brychta

Gerard Mora Puchalt

Aine Mccarthy

Various examples are directed to methods and system of managing a sensor. A measurement system may receive from the host device, a first register map describing a first configuration of the measurement system for the first sensor. The first configuration may indicate a first measurement frequency for the first sensor. The measurement system may configure a switch matrix to provide a first excitation signal to the first sensor. The measurement system may configure the switch matrix to connect an analog-to-digital converter (ADC) of the measurement system to the first sensor. The measurement system may sample a first raw sensor signal from the first sensor with the ADC at a first measurement frequency described by the first configuration. The measurement system may generate first digital measurement data based at least in part on the first raw sensor signal and send the first digital measurement data to the host device.

Measurement system

Various examples are directed to systems and methods for managing a sensor. A measurement system may receive, from a host device, a first register map describing a first configuration of a measurement system. The first configuration may be associated with a first sensor. The measurement system may compare the first register map to an error rule set indicating inconsistent register map arrangements. After comparing the first register map to the error rule set, the measurement system may configure a switch matrix of the measurement system to sample the first sensor according to the first configuration of the measurement system. The measurement system may receive a plurality of samples from a first sensor and generate first digital measurement data based at least in part on the plurality of samples.

A fault detection scheme can include use of a relatively high injection impedance between an input port for analog measurements from a sensor and a stimulus generation circuit controlled in coordination with analog measurement. The stimulus generation circuit can provide a stimulus signal through the injection impedance. A magnitude of the injection impedance can be specified relative to a source impedance associated with a source (e.g., a sensor or other device) coupled to the input port. For example, a magnitude of the injection impedance can be specified to be larger than the source impedance or the injection impedance magnitude can be specified to be a multiple of the source impedance.

ADC input circuit sensing for fault detection

Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.

Time interleaved filtering in analog-to-digital converters

A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Input current cancellation scheme for fast channel switching systems

An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.

Method and apparatus for separating the reference current from the input signal in sigma-delta converter

A sigma-delta analog-to-digital converter ('&#x3a3;&#x394; ADC') may include a loop filter, ADC, a feedback digital-to-analog converter ('DAC'), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a &#x3a3;&#x394; ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the &#x3a3;&#x394; ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.

Stability correction for a shuffler of a &#x3a3;-delta ADC

Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Synchronous analog to digital conversion system and method

A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater than full scale input range of the analog to digital converter in an interval shorter than the period of the predetermined output rate of the analog to digital converter and adjusting the gain of the programmable gain amplifier to reduce the output below the full scale of the analog to digital converter at a rate faster than the predetermined output rate of the ADC.

Rapid response current measurement system and method

A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Amplifier gain calibration system and method

A signal processing circuit comprising an ADC ( ) to which differential signals and pseudo-differential signals are switched through two multiplexors ( ) and ( ). Positive input signals are buffered to a positive input terminal ( ) of the ADC ( ) through a buffer ( ). Negative input signals are buffered through a conditioning circuit ( ) to a negative input terminal ( ) of the ADC ( ). The conditioning circuit ( ) comprises a buffer circuit ( ) having a buffer ( ), through which input signals are selectively buffered to the negative input terminal ( ) of the ADC ( ), and a bypass circuit ( ) which bypasses the buffer circuit ( ) for selectively passing input signals unbuffered to the negative input terminal ( ) of the ADC . First and second primary switches ( ) and ( ) are selectively operated in response to a primary switching signal from a control circuit ( ) for selecting one of the buffer circuit ( ) and the bypass circuit ( ) in response to channel select signals for the multiplexors ( ) and ( ) so that input signals, the voltage of which falls outside the operating voltage of the buffer ( ) are passed unbuffered directly to the negative input terminal ( ) through the bypass circuit ( ). The control circuit ( ) instead of being responsive to a channel select signal may be arranged to be responsive to the voltage of the input signals for operating the first and secondary primary switches ( ). Two conditioning circuits ( ) may be provided one for each input terminal to the ADC ( ).

Conditioning circuit for selectively buffering an input signal to a signal processing circuit, and a signal processing circuit incorporating the conditioning circuit

A circuit used for testing an integrated circuit including a chop circuit. A source of a test signal coupled to a first pair of pins of the integrated circuit. A test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit. A chop circuit controller produces a control signal and for feeding such control to the chop circuit and the test signal measuring device. In response to the control signal, the chop circuit couples the first pair of pins to the second pair of pins with a first polarity during a first period of time and couples the first pair of pins to the second pair of pins with an opposite polarity during a second period of time.

Circuit for testing an integrated circuit

An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Analog-to-digital conversion system

A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Digital filtering system

An invalid reference detection circuit formed on a semiconductor chip having: reference input terminals adapted for coupling to a reference source external to the chip; a local reference source; and comparison circuit. The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and to produce an output signal indicative of the detected invalid condition. The invalid condition at the reference input terminals may be an open circuit condition at at least one of the reference input terminals, a condition when the voltage across the reference input terminals is below a predetermined minimum voltage level, a condition when the voltage across the reference input terminals is above a predetermined maximum voltage level, and/or a short circuit condition. An analog/digital conversion system is formed on a semiconductor chip together with the invalid reference detection circuit. The reference input terminals are adapted for coupling to the reference source external to the chip to the conversion circuitry to provide a reference for such conversion circuitry.

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Raheen, Ireland

Adrian Sherry