Qualcomm Incorporated

Arm Limited

Adrian Montero

Joseph Michael Pusdesris

Paul Kitchin

Huzefa Sanjeliwala

Conrado Blasco

Klas Magnus Bruce

Miles Robert Dooley

Alexander Cole Shulyak

Chris Abernathy

Yasuo Ishii

Abhishek Raja

Michael Filippo

Karthik Sundaram

Barry Duane Williamson

Balaji Vijayan

Vikas Kumar Sinha

Pradeep Kanapathipillai

Prarthna Santhanakrishnan

Roshan Sreekumar Nair

Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.

Compressing data portions in a translation lookaside buffer

Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices

Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices

An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.

Latency management in synchronization events

Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

Data processing apparatus and method for generating prefetches

An apparatus and method are provided. The apparatus comprises storage circuitry to store a plurality of data elements. Processing circuitry executes a stream of instructions comprising access instructions that access some of the data elements at given locations. Training circuitry determines a pattern of the given locations based on the access instructions. Prefetch circuitry performs prefetches based on the pattern and filter circuitry filters the access instructions used by the training circuitry to determine the pattern by including discontinuous access instructions whose given location raises a discontinuity with the given location of a previous access instruction. In this way, it is possible to perform prefetching by calculating, rather than guessing, at a cumulative stride between the access instructions.

Determining prefetch patterns with discontinuous strides

The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.

Cache storage techniques

Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.

Storage circuitry request tracking

A data processing systemincludes an address translation cacheto store a plurality of address translation entries. Eviction control circuitryselects a victim entry for eviction from address translation cacheusing an eviction control parameter. The address translation cachecan store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

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Austin, TX, United States of America

Adrian Montero