Microsoft Technology Licensing, LLC

Adrian Michael Caulfield

Eric S Chung

Michael Konstantinos Papamichael

Douglas Christopher Burger

Andrew Richard Putnam

Blake Douglas Pelton

Derek Chiou

Sitaram V Lanka

Stephen Francis Heil

Doug Burger

Yi Xiao

Ang Li

Shlomi Alkalay

Prashant Ranjan

Alexey Lavrov

Mohammad Saifee Dohadwala

Stephen F Heil

Derek T Chiou

Techniques and algorithms for monitoring network congestion and for triggering a flow to follow a new path through a network. The network is monitored, and network feedback data is acquired, where that data indicates whether the network is congested. If the network is congested, a feedback-driven algorithm can trigger a flow to follow a new path. By triggering the flow to follow the new path, congestion in the network is reduced. To identify congestion, the feedback data is analyzed to determine whether flows are colliding. The feedback-driven algorithm determines that a network remapping event is to occur in an attempt to alleviate the congestion. A flow is then selected to be remapped to alleviate the congestion.

Feedback-based dynamic network flow remapping

A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.

Masked packet checksums for more efficient digital communication

A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

Generating a synchronous digital circuit from a source code construct defining a function call

Systems and methods that provide for transmission of messages among nodes (e.g., acceleration components configurable to accelerate a service) using a time-synchronized transport layer (TSL) protocol are provided. An example method, in a network comprising at least a first node, a second node, and a third node, includes each of the at least the first node, the second node, and the third node synchronizing a respective clock to a common clock. The method further includes each of the at least the first node, the second node, and the third node scheduling data transmission in the network in a manner such that at a particular time in reference to the common clock each of the at least the first node, the second node, and the third node is scheduled to receive data from only one of the first node, the second node, or the third node.

Systems and methods for nodes communicating using a time-synchronized transport layer

A multi-threaded imperative programming language includes language constructs that map to circuit implementations. The constructs can include a condition statement that enables a thread in a hardware pipeline to wait for a specified condition to occur, identify the start and end of a portion of source code instructions that are to be executed atomically, or indicate that a read-modify-write memory operation is to be performed atomically. Source code that includes one or more constructs mapping to a circuit implementation can be compiled to generate a circuit description. The circuit description can be expressed using hardware description language (HDL), for instance. The circuit description can, in turn, be used to generate a synchronous digital circuit that includes the circuit implementation. For example, HDL might be utilized to generate an FPGA image or bitstream that can be utilized to program an FPGA that includes the circuit implementation associate with the language construct.

Generating synchronous digital circuits from source code constructs that map to circuit implementations

Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit ('SDC') that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.

Generating a debugging network for a synchronous digital circuit during compilation of program source code

A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. '&', '+') is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.

Lookup table optimization for programming languages that target synchronous digital circuits

A multi-threaded programming language and compiler generates synchronous digital circuits that maintain thread execution order by generating pipelines with code paths that have the same number of stages. The compiler balances related code paths within a pipeline by adding additional stages to a code path that has fewer stages. Programming constructs that, by design, allow thread execution to be re-ordered, may be placed in a reorder block construct that releases threads in the order they entered the programming construct. First-in-first-out (FIFO) queues pass local variables between pipelines. Local variables are popped from FIFOs in the order they were pushed, preserving thread execution order across pipelines.

Language and compiler that generate synchronous digital circuits that maintain thread execution order

Aspects extend to methods, systems, and computer program products for partially reconfiguring acceleration components. Partial reconfiguration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During partial reconfiguration, connectivity can be maintained for any other functionality at the acceleration component untouched by the partial reconfiguration. Partial reconfiguration is more efficient to deploy than full reconfiguration of an acceleration component.

Partially reconfiguring acceleration components

A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.

Hardware implemented load balancing

Systems and methods for monitoring and steering service requests to acceleration components are provided. An example method in a system comprising a host configured to send messages, corresponding to a service, to any of a set of acceleration components may include tracking an input buffer occupancy corresponding to each of the set of acceleration components. The method may further include, upon a first input buffer occupancy of a first acceleration component from among the set of the acceleration components meeting a predetermined criterion, generating a first penalty value for the first acceleration component based at least on the first input buffer occupancy associated with the first acceleration component, and comparing a second value indicative of an availability of the second acceleration component to receive messages from the host to a second dynamically updated value to determine whether the host can send a next message to the second acceleration component.

Monitoring and steering service requests to acceleration components

Active intelligent message filtering can be utilized to provide error resiliency, thereby allowing messages to be received without traditional error detection, and, in turn, avoiding the inefficiency of retransmission of network communications discarded due to network transmission errors detected by such traditional error detection mechanisms. Network transmission errors can result in the receiving application receiving messages that appear to comprise values that differ from the values originally transmitted by the transmitting application. Based on the inaccuracy tolerance applicable to the transmitting and receiving applications, rules can be applied to actively intelligently filter the received messages to replace the received values with the replacement values according to the rules. In such a manner, the receiving application can continue to receive usable data from the transmitting application without any error detection at lower network communication levels.

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Woodinville, WA, United States of America

Adrian Michael Caulfield