Silicon Laboratories Inc.

Cirrus Logic Inc.

Maxim Integrated Products, Inc.

Adrian Maxim

James T Kao

Edmund Mark Schneider

Charles D Thompson

Mitchell Reid

Melvin L Hagge

Baker Scott, Iii

Ramin Khoini-Poorfard

Richard A Johnson

Jaideep Prakash

A receiver () includes a mixing digital-to-analog converter (DAC) (), a direct digital frequency synthesizer (DDFS) (A) and an interface (D). The mixing DAC () includes a radio frequency (RF) transconductance section () and a switching section (). The RE transconductance section () includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section () is coupled to the RF transconductance section () and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (). The interface (D) is coupled to the DDFS (A) and is configured to align the bits provided by the DDFS (A) with a first clock signal.

Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures

A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Providing a low phase noise reference signal

A receiver () includes a first mixing digital-to-analog converter (DAC) (), a second mixing DAC (), a direct digital frequency synthesizer (DDFS) (), a phase correction circuit (), a selectable load () and a magnitude correction circuit (). The first mixing DAC () includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC () includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS () is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit () is configured to provide a phase correction signal to a control input of the DDFS (). The first selectable load () includes an input coupled to the output of the first mixing DAC () and a control input. The magnitude correction circuit () is configured to provide a first magnitude correction signal to the control input of the first selectable load ().

Techniques for performing gain and phase correction in a complex radio frequency receiver

A receiver () includes a mixing digital-to-analog converter (DAC) (), a direct digital frequency synthesizer (DDFS) (), and a clock circuit (). The mixing DAC () includes a radio frequency (RF) transconductance section () and a switching section (). The RF transconductance section () includes an input configured to receive an RF signal. The switching section is coupled to the RF transconductance section () and includes inputs, configured to receive bits associated with a digital local oscillator (LO) signal, and an output. The DDFS () includes outputs, configured to provide the bits associated with the digital LO signal to the inputs of the switching section (), and a first clock input, configured to receive a first clock signal that sets a sample rate for the digital LO signal The clock circuit () is configured to provide the first clock signal to the first clock input of the DDFS () at a frequency that is based on a selected channel.

Power consumption reduction techniques for an RF receiver implementing a mixing DAC architecture

A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.

Receiver architectures utilizing coarse analog tuning and associated methods

A receiver () includes a mixing digital-to-analog converter (DAC) (A), a direct digital frequency synthesizer (DDFS) () and a dynamic element matching (DEM) circuit (). A DAC of the mixing DAC (A) is implemented as a segmented DAC having a thermometer encoded DAC section (A) and a binary encoded DAC section (B). The DDFS () includes outputs configured to provide bits associated with a digital LO signal to inputs of a switching section (A,B) of the mixing DAC (A). The DEM circuit () is coupled between the outputs of the DDFS () and the inputs of the switching section (A) that are associated with the thermometer encoded DAC section (A). The DEM circuit () is configured to scramble the bits provided to the thermometer encoded DAC section (A).

Mixing DAC architectures for a radio frequency receiver

High frequency laser diode (LD) and electro-absorption modulator (EAM) integrated circuit drivers using a cascaded output switch architecture that increases the output current and voltage edge speed and reduces the peaking and ringing of the output waveform, thus improving the deterministic jitter performance. Also disclosed is a method and apparatus that provides a modulation current dependence of both turn-on and turn-off driving currents that lead to an optimal compromise between the edge speed and output overshoot for a wide range of modulation currents. A PTAT temperature dependence of both voltage swing and current level in the predriver assures a low variation of the overshoot and rise/fall time over a wide temperature range. Using the cascaded output switch architecture provides an easy way of on-chip summation of the modulation and bias currents. Biasing the cascode device with a supply and modulation current dependent base voltage provides an optimum headroom output switch.

Systems and methods for using cascoded output switch in low voltage high speed laser diode and EAM drivers

Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques

A loop filter device and method for implementing a loop filter for a phase locked loop (&ldquo;PLL&rdquo;) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

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Austin, TX, United States of America

Adrian Maxim