Cadence Design Systems, Inc.

Adrian Luigi Leuciuc

William Pierce Evans

Methods and systems provide a multiplexing cell and a multiplexing cell system for data serialization. The multiplexing cell may be dynamic D-type flip flop having a single phase clock signal (CLK) and a select input (SEL). An input to the multiplexing cell may be passed to an output if CLK is high and SEL are both high. Otherwise, the output of each multiplexing cell may be in a high impedance state. A multiplexing cell system may include one or more of the multiplexing cells and be configured to provide serialization of input data at high data rates with reduced power consumption. Sub-rate clocks, which may be used by at least a portion of a serialization chain, may reduce power consumption allow for less complex clock generation and distribution circuitry. The multiplexing cell and/or multiplexing cell system find application in, among other things, equalization to offset effects of channel imperfections.

Dynamic flip-flop and multiplexer for sub-rate clock data serializer

A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment. Each timing skew factor is generated based adaptively on the output samples for a selective combination of segments including at least one preceding and at least one succeeding sample segment. A plurality of timing control units respectively coupled to the ADC channels adjust time delays for the sampling clock within respective sample segments responsive to the timing skew factors, thereby substantially aligning the sample segments with the sampling clock.

System and method for interleaved analog-to-digital conversion having scalable self-calibration of timing

An analog to digital converting system () includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADCADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) () therein. The system further includes a sample and hold circuit () coupled to the parallel ADCs by a conductive interconnect wiring pattern (). The sample and hold circuit includes a sampling switch () and a hold capacitance formed by the parallel combination of a hold capacitor () and the distributed parasitic capacitance () of the conductive interconnect wiring pattern (). During the hold phase of the sample and hold circuit, charge is redistributed from the hold capacitance to all of the capacitors () of the capacitor DAC, which serve as a secondary hold capacitance.

Parallel analog to digital converter architecture with charge redistribution and method thereof

An adjustable gain amplifier system having cleanly adjustable and stable linearized gain is provided for amplifying an input signal. The system generally comprises a main amplifier and a linearized transconductance amplifier coupled thereto, which generates an amplified current signal in response to the input signal according to a variably defined transconductance factor. The linearized transconductance amplifier includes a linearized transconductance portion and a translinear current amplifier portion coupled thereto. The linearized transconductance portion generates an intermediate current signal based upon a voltage of the input signal, and forms an unswitched resistor-based conduction path for that intermediate current signal. The translinear current amplifier portion forms a translinear loop section for amplifying the intermediate current signal to generate the amplified current signal. The translinear current amplifier portion is selectively reconfigurable to correspondingly adjust the transconductance factor, wherein the linearized gain is adjustably defined according to the adjusted transconductance factor.

Adjustable gain amplifier system having cleanly adjustable and stable linearized gain

The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

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Frederick, MD, United States of America

Adrian Luigi Leuciuc