Intel Corporation

Adrian L Carbine

Gary L Brown

Donald D Parker

Frank S Smith

Glenn J Hinton

Rajesh Kumar

Michael W Rhodehamel

Chan W Lee

Ashwani Kumar Gupta

Bradley D Hoyt

Anthony C Miller

James A Wilson

Sumeet Agrawal

Derek B Feltham

An instruction decoder that issues new instructions by driving a machine bus ( ) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents ( ) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer ( ) chooses between several sources of opcode and operand fields and routes them to the machine bus ( ) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic ( ).

Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit

A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Control register bus access through a standardized test access port

A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.

Instruction length decoder for generating output length indicia to

A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.

Packing valid micro operations received from a parallel decoder into

A split queue system for a decoder that supplies one or more micro-operations and data associated with the micro-operations. A main queue is coupled to receive one or more micro-operations from the decoder, and supply it to a next processing stage to provide a process micro-operation. A shadow queue is coupled to receive data associated with the micro-operation, in the same cycle that the micro-operation is supplied to the main queue. A control circuit is coupled to the main queue for issuing micro-operation from the main queue into the next processing stage in a first cycle, and in a second cycle issuing, the micro-operation therefrom. Also in the second cycle, the control circuit issues the data associated with the micro-operation from the shadow queue, so that the data is synchronized with its associated processed micro-operation.

Decoder having a split queue system for processing intstructions in a

A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.

Decoder for decoding multiple instructions in parallel

A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

Scan mechanism for monitoring the state of internal signals of a VLSI

An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

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Hillsboro, OR, United States of America

Adrian L Carbine